LTC4258 LINER [Linear Technology], LTC4258 Datasheet - Page 23

• Manufacturer Part Number: LTC4258
• Description: Quad IEEE 802.3af Power over Ethernet Controller with Integrated Detection
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
it is sending its address, it monitors the SDAIN pin to see
if another device is sending an address at the same time
using standard I
sending a 1 and reads a 0 on the SDAIN pin on the rising
edge of SCL, it assumes another device with a lower
address is sending and the LTC4258 immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC4258 will
stop pulling down the INT pin. When the INT pin is released
in this way or if a 1 is written into the Clear Interrupt pin bit
(bit 6 of register 1Ah), the condition causing the LTC4258
to pull the INT pin down must be removed before the
LTC4258 will be able to pull INT down again. This can be
done by reading and clearing the event registers or by
writing a 1 into the Clear All Interrupts bit (bit 7 of register
1Ah). The state of the INT pin can only change between I
transactions, so an interrupt is cleared or new interrupts
are generated after a transaction completes and before
new I
of the alert response address can be used instead of the
INT pin if desired. If any device acknowledges the alert
response address, then the INT line, if connected, would
have been low.
System Software Strategy
Control of the LTC4258 hinges on one decision, the
LTC4258’s operating mode. The three choices are de-
scribed under Operating Modes. In Auto mode the LTC4258
can operate autonomously without direction from a host
controller. Because LTC4258s running in Auto mode will
power every valid PD connected to them, the PSE must
have 15.4W/port available. To reduce the power require-
ments of the –48V supply, PSE systems can track power
usage, only turning on ports when sufficient power is
available. The IEEE describes this as a power allocation
algorithm and places two limitations: the PSE shall not
power a PD unless it can supply the guaranteed power for
that PD’s class (see Table 2) and power allocation may not
2
C bus communication commences. Periodic polling
2
C bus arbitration. If the LTC4258 is
U
U
W
U
2
C
be based solely on a history of each PD’s power consump-
tion. In order for a PSE to implement power allocation, the
PSE’s processor/controller must control whether ports
are powered—the LTC4258 cannot be allowed to operate
in Auto mode. Semiauto mode fits the bill as the LTC4258
automatically detects and classifies PDs, then makes this
information available to the host controller, which de-
cides to apply power or not. Operating the LTC4258 in
Manual mode also lets the controller decide whether to
power the ports but the controller must also control
detection and classification. If the host controller oper-
ates near the limit of its computing resources, it may not
be able to guide a Manual mode LTC4258 through detect,
class and port turn-on in less than the IEEE mandated
maximum of 950ms.
In a typical PSE, the LTC4258s will operate in Semiauto
mode as this allows the controller to decide to power a
port without unduly burdening the controller. With an
interrupt mask of F4h, the LTC4258 will signal to the host
after it has successfully detected and classed a PD, at
which point the host can decide whether enough power is
available and command the LTC4258 to turn that port on.
Similarly, the LTC4258 will generate interrupts when a
port’s power is turned off. By reading the LTC4258’s
interrupt register, the host can determine if a port was
turned off due to overcurrent (t
because the PD was removed (Disconnect event). The
host then updates the amount of available power to reflect
the power no longer consumed by the disconnected PD.
Setting the MSB of the interrupt mask causes the LTC4258
to communicate fault conditions caused by failures within
the PSE, so the host does not need to poll to check that the
LTC4258s are operating properly. This interrupt driven
system architecture provides the controller with the final
say on powering ports at the same time, minimizing the
controller’s computation requirements because inter-
rupts are only generated when a PD is detected or on a
fault condition.
START
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LTC4258
ICUT
faults) or
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