LTC4261 LINER [Linear Technology], LTC4261 Datasheet - Page 14

• Manufacturer Part Number: LTC4261
• Description: Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring
• Manufacturer: LINER [Linear Technology]

LTC4261/LTC4261-2
APPLICATIONS INFORMATION
If any of the above conditions is violated before the start-up
delay expires, C
sequence is restarted. After all the conditions are validated
throughout the start-up delay, the ON pin is then checked.
If it is high, the FET will be turned on. Otherwise, the FET
will be turned on when the ON pin is raised high or the FET
ON bit D3 in the CONTROL register is set to “1” through
the I
The FET turn-on sequence follows by charging an external
capacitor at the SS pin (C
and the voltage at SS (V
(I
the GATE reaches the FET threshold voltage, the inrush
current starts to fl ow through the FET and a current
(I
and through an external capacitor (C
RAMP and V
corresponds to I
RAMP pin voltage is regulated at 1.1V and the ramp rate
of V
The ramp rate of V
current:
If C
0V to 2.56V in about 220µs.
When V
the GATE pin and pulls the GATE up to V
illustrates the start-up sequence of the LTC4261/
LTC4261-2.
During board insertion and input power step, an internal
clamp turns on to hold the RAMP pin low. Capacitor C
and resistor R
proper operation, R
recommended value of C
14
GATE(UP)
RAMP
I
dI
INRUSH
SS
OUT
2
INRUSH
C interface.
is absent, an internal circuit pulls the SS pin from
) of 20µA· V
dt
determines the inrush current:
OUT
) of 11.5µA· V
= 20
OUT
= 20
is ramped down to V
F
. The SS voltage is clamped to 2.56V, which
TMR
suppress the noise at the RAMP pin. For
µA
GATE(UP)
µA
SS
•
is quickly discharged and the turn-on
F
SS
C
C
•
/2.56V fl ows out of the RAMP pin
• C
R
L
C
C
SS
determines dI/dt of the inrush
L
R
= 11.5µA and I
R
F
SS
/2.56V for GATE pull-up. When
SS
•
is 3 • C
should not exceed 50µs. The
) with a 10µA pull-up current
256
) is converted to a current
ms C
1
µF
R
R
.
•
EE
) connected between
, I
SS
RAMP
GATE
GATEH
= 20µA. The
returns to
. Figure 3
F
Power Good Monitors
When V
GATE pulls above V
signal is latched and a series of three delay cycles are
started as shown in Figure 3. When the fi rst delay cycle
with a duration of 2t
power good signal to turn on the fi rst module. When the
second delay cycle (2t
as a power good signal to turn on the second module. The
third delay cycle with a duration of 4t
Before the third delay cycle expires, the PGI pin must be
pulled low by an external supply monitor (such as the
LTC2900 in Figure 2) to keep the FET on. Otherwise, the
FET is turned off and the power bad fault (PBAD) is logged
in the FAULT register. The 2t
charging C
with a 12mA current when TMR reaches 2.56V. For the
4t
C
PGIO are reset in all FET turn-off conditions except the
overvoltage fault.
Turn-Off Sequence and Auto-Retry
In any of the following conditions, the FET is turned off
by pulling down GATE with a 110mA current, and C
and C
1. The ON pin is low or the ON bit in the CONTROL reg-
2. The EN pin is high.
3. The voltage at UVL is lower than 2.291V and the volt-
4. The voltage at OV is higher than 1.77V (overvoltage
5. The voltage at V
TMR
D
ister is set to 0.
age at UVH is lower than 2.56V (undervoltage fault).
fault).
lockout).
timer delay, the charging and discharging currents of
TMR
are both 5µA. The power good signals at PG and
DS
are discharged with 12mA currents.
TMR
of the pass transistor falls below 1.77V and
with a 5µA current and discharging C
IN
D
Z
is lower than 9V (V
D
expires, the PG pin pulls low as a
– 1.2V, an internal power good
) expires, the PGIO pin pulls low
D
timer delay is obtained by
D
is for PGI check.
IN
undervoltage
42612fb
TMR
SS