LTC4265 LINER [Linear Technology], LTC4265 Datasheet - Page 3

• Manufacturer Part Number: LTC4265
• Description: IEEE 802.3at High Power PD Interface Controller with 2-Event Classifi cation Recognition
• Manufacturer: LINER [Linear Technology]

ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
PARAMETER
Operating Input Voltage
ON/UVLO Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
SUPPLY CURRENT
Supply Current at 60V
Class 0 Current
SIGNATURE
Signature Resistance
Invalid Signature Resistance, SHDN Invoked
Invalid Signature Resistance During Mark Event (Notes 6, 7)
CLASSIFICATION
Class Accuracy
Classifi cation Stability Time
NORMAL OPERATION
Inrush Current
Power FET On Resistance
Power FET Leakage Current at V
DIGITAL INTERFACE
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
PWRGD, T2PSE Voltage Output Low
PWRGD, T2PSE Leakage Current
PWRGD Voltage Output Low
PWRGD Voltage Clamp
PWRGD Leakage Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltages are with respect to V
Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.
Note 4: PWRGD voltage clamps at 14V with respect to V
Note 5: Input voltage specifi cations are defi ned with respect to LTC4265
pins and meet IEEE 802.3af/at specifi cations when the input diode bridge
is included.
Signature Range
Classifi cation Range
Turn-On Voltage
Undervoltage Lock Out
Overvoltage Lock Out
OUT
IN
pin unless otherwise noted.
CONDITIONS
At GND Pin (Note 5)
State Machine Reset for 2-event Classifi cation
Measured at GND Pin
GND = 17.5V, No R
1.5V ≤ GND ≤ 9.8V (Note 6)
1.5V ≤ GND ≤ 9.8V, V
10mA < I
GND Pin Step to 17.5V, R
3.5% of Ideal Value (Notes 8, 9)
GND = 54, V
Tested at 600mA into V
GND = SHDN = V
GND = 9.8V, SHDN = 9.65V
Tested at 1mA, GND = 54V. For T2PSE, Must Complete
2-event Classifi cation to See Active Low.
Pin Voltage Pulled 57V, GND = V
Tested at 0.5mA, GND = 52V, V
is with Respect to V
Tested at 2mA, V
V
PWRGD
OUT
= 11V, V
CLASS
.
A
= 25°C.
OUT
< 40mA, 12.5V < GND < 21V (Note 8, 9)
= 3V
OUT
OUT
OUT
The
CLASS
OUT
= 57V
= V
= 0V, Voltage with Respect to V
SHDN
l
OUT
IN
denotes the specifi cations which apply over the full operating
Resistor
CLASS
= 0V, GND = 54V
= 3V (Note 6)
, GND = 54V
Note 6: Signature resistance is measured via the ΔV/ΔI method with a
minimum ΔV of 1V. The LTC4265 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7: An invalid signature after the 1st classifi cation event is mandated
by IEEE 802.3at standard. See Applications Information.
Note 8: Class accuracy is with respect to the ideal current defi ned as
1.237/R
Note 9: This parameter is assured by design and wafer level testing.
OUT
= 30.9, I
IN
= 0
= 48V, Output Voltage
CLASS
CLASS
and does not include variations in R
Within
OUT
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
23.25
MIN
12.5
30.0
2.57
100
1.5
4.1
1.4
60
12
3
0.70
TYP
100
71
CLASS
LTC4265
resistance.
MAX
±3.5
37.2
5.40
1.35
0.40
0.45
0.15
16.5
180
9.8
1.0
0.4
60
21
26
11
11
1
1
1
1
UNITS
3
4265f
mA
mA
mA
ms
kΩ
kΩ
kΩ
kΩ
μA
μA
μA
%
Ω
V
V
V
V
V
V
V
V
V
V
V
V
V
V