LTC5598IUF LINER [Linear Technology], LTC5598IUF Datasheet - Page 10

• Manufacturer Part Number: LTC5598IUF
• Description: 5MHz to 1600MHz High Linearity Direct Quadrature Modulator
• Manufacturer: LINER [Linear Technology]

LTC5598
be the signal source for the LTC5598. A reconstruction
fi lter should be placed between the DAC output and the
LTC5598’s baseband inputs.
In Figure 2 a typical baseband interface is shown, using
a fi fth-order lowpass ladder fi lter.
For each baseband pin, a 0 to 1V swing is developed
corresponding to a DAC output current of 0mA to 20mA.
The maximum sinusoidal single side-band RF output power
is about +7.3dBm for full 0V to 1V swing on each I- and
Q- channel baseband input (2V
LO Section
The internal LO chain consists of poly-phase phase shifters
followed by LO buffers. The LOP input is designed as a
single-ended input with about 50Ω input impedance. The
LOM input should be terminated with 50Ω through a DC
blocking capacitor.
The LOP and LOM inputs can be driven differentially in
case an exceptionally low large-signal output noise fl oor
is required (see graph 5598 G20b).
A simplifi ed circuit schematic for the LOP, LOM, CAPA
and CAPB inputs is given in Figure 3. A feedback path is
implemented from the LO buffer outputs to the LO inputs
in order to minimize offsets in the LO chain by storing the
offsets on C5, C7 and C8 (see Figure 10). Optional capacitor
C8 improves the image rejection below 100MHz (see
graph 5598 G20a). Because of the feedback path, the input
impedance for P
for P
frequency range. In Table 2, the LOP port input impedance
vs frequency is given for EN = High and P
EN = Low and P
APPLICATIONS INFORMATION
10
0mA TO 20mA
0mA TO 20mA
LO
DAC
Figure 2. Baseband Interface with 5th Order Filter
and 0.5V
= 10dBm for the lower part of the operating
CM
LO
LO
R1A
100
R1B
100
DAC (Only I Channel is Shown)
= 0dBm, the input impedance is given
= 0dBm is somewhat different than
C1
L1A
L1B
GND
PP, DIFF
C2
L2A
L2B
).
C3
LO
0.5V
0.5V
= 0dBm. For
DC
DC
R2A
100
R2B
100
BBMI
BBPI
5598 F02
LOP
in Table 3. In Table 4 and 5, the LOP port input impedance
is given for EN = High and Low under the condition of
P
for the standard demo board (schematic is shown in
Figure 10) when the LOM port is terminated with 50Ω to
GND. The values of L1, L2, C9 and C10 are chosen such
that the bandwidth for the LOP port of the standard demo
board is maximized while meeting the LO input return loss
S
Table 2. LOP Port Input Impedance vs Frequency for EN = High
and P
LO
11, ON
FREQUENCY
= 10dBm. Figure 4 shows the LOP port return loss
(MHz)
LO
1000
1250
1500
1800
100
200
400
800
0.1
16
30
60
1
2
4
8
= 0dBm (LOM AC Coupled With 50Ω to Ground).
< –10dB.
Figure 3. Simplifi ed Circuit Schematic for the
LOP, LOM, CAPA and CAPB Inputs.
IMPEDANCE
89.9 – j95.4
60.4 – j60.6
54.8 – j35.8
43.6 – j24.4
37.9 – j17.3
31.8 – j12.4
333 – j10.0
318 – j59.9
285 – j94.7
227 – j120
154 – j124
23.6 – j8.2
19.8 – j5.5
16.0 – j1.8
13.6 + j2.4
12.1 + j7.3
LO INPUT
V
CC1
CAPA
LOM
REFLECTION COEFFICIENT
0.739
0.737
0.728
0.708
0.678
0.611
0.420
0.489
0.261
0.235
0.266
0.374
0.437
0.515
0.574
0.618
MAG
+
2.8V
(4.3V IN
SHUTDOWN)
ANGLE
–10.6
–18.7
–33.0
–41.3
–51.5
–89.9
–113
–137
–156
–165
–175
–0.5
–3.3
–6.1
5598 F03
174
162
CAPB
5598f