AD7834SQ AD [Analog Devices], AD7834SQ Datasheet
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AD7834SQ
Manufacturer Part Number
AD7834SQ
Description
LC2MOS Quad 14-Bit DAC
Manufacturer
AD [Analog Devices]
Datasheet
1.AD7834SQ.pdf
(16 pages)
a
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Four 14-Bit DACs in One Package
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
FSYNC
PAEN
SCLK
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
PA0
PA1
PA2
PA3
PA4
DIN
AD7834 FUNCTIONAL BLOCK DIAGRAM
CONVERTER
AD7834
SERIAL-TO-
PARALLEL
CONTROL
ADDRESS
DECODE
LOGIC
&
V
AGND
CC
V
REGISTER
REGISTER
REGISTER
REGISTER
DD
INPUT
INPUT
INPUT
INPUT
DGND
1
2
3
4
V
SS
LATCH
LATCH
LATCH
LATCH
DAC 1
DAC 2
DAC 3
DAC 4
LDAC
V
REF
(–) V
DAC 3
DAC 1
DAC 2
DAC 4
REF
DSG
(+)
X1
X1
X1
X1
V
V
V
V
CLR
OUT
OUT
OUT
OUT
1
2
3
4
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of 8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or V
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF and DAC channel address pins, A0–A2.
With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
V
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within 2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
OUT
BYSHF
DB13
DB0
WR
CS
A0
A1
A2
1–V
OUT
AD7835 FUNCTIONAL BLOCK DIAGRAM
AD7835
ADDRESS
BUFFER
DECODE
INPUT
4, to the user-defined voltage level on the Device
AGND
14
V
CC
V
REGISTER
REGISTER
REGISTER
REGISTER
DGND
DD
INPUT
INPUT
INPUT
INPUT
1
2
3
4
AD7834/AD7835
V
SS
Quad 14-Bit DAC
LDAC
LATCH
LATCH
LATCH
LATCH
DAC 1
DAC 2
DAC 3
DAC 4
V
V
REF
REF
CC
© Analog Devices, Inc., 1995
(–)A V
(–)B V
DAC 1
DAC 2
DAC 3
DAC 4
to permit up to 32
REF
REF
(+)A
(+)B
Fax: 617/326-8703
LC
DSG A
DSG B
X1
X1
X1
X1
2
MOS
V
V
V
V
CLR
OUT
OUT
OUT
OUT
1
3
2
4