AD7834SQ AD [Analog Devices], AD7834SQ Datasheet - Page 11

• Manufacturer Part Number: AD7834SQ
• Description: LC2MOS Quad 14-Bit DAC
• Manufacturer: AD [Analog Devices]

REV. A
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 15. It is capable of driving a load of 10 k in
parallel with 200 pF. G
used to control the power on voltage present at V
G
to the user defined voltage present at the DSG pin.
Power-On with CLR Low, LDAC High
The output stage of the AD7834/AD7835 has been designed to
allow output stability during power-on. If CLR is kept low dur-
ing power-on, then just after power is applied to the part, the
situation is as depicted in Figure 16. G
while G
V
R. R is a thin-film resistor between DSG and V
put amplifier is connected as a unity gain buffer via G
DSG voltage is applied to the buffer input via G
ers output is thus at the same voltage as the DSG pin. The out-
put stage remains configured as in Figure 16 until the voltage at
V
amplifier has enough headroom to handle signals at its input
and has also had time to settle. The internal power-on circuitry
opens G
in Figure 17. Now the output amplifier is connected in unity
gain mode via G
the noninverting input via G
Figure 15. Block Diagram of AD7834/AD7835 Output Stage
OUT
DD
2
Figure 17. Output Stage with V
are also used in conjunction with the CLR input to set V
and V
is kept within a few hundred millivolts of DSG via G
2
3
, G
and G
DAC
DAC
Figure 16. Output Stage with V
DAC
SS
3
reaches approximately 10 V. By now the output
and G
5
4
and closes G
and G
G
G
G
G
G
G
5
1
1
1
2
2
2
DSG
DSG
DSG
are closed.
1
6
. The DSG voltage is still applied to
to G
2
. This voltage appears at V
6
4
G
G
G
G
G
G
are transmission gates that are
and G
3
3
3
5
5
5
DD
R
R
R
6
1
. This situation is shown
, G
> 10 V and CLR Low
G
G
G
G
G
G
6
6
4
6
4
4
4
and G
DD
< 10 V
OUT
2
. The amplifi-
OUT
6
. The out-
are open
. G
V
V
V
3
OUT
OUT
OUT
and the
OUT
1
and
5
.
OUT
and
–11–
V
of G
gain buffer.
Power-On with LDAC Low, CLR High
In many applications of the AD7834/AD7835 LDAC will be
kept continuously low, thus updating the DAC after each valid
data transfer. If LDAC is low when power is applied, then G
closed and G
to the input of the output amplifier. G
and G
buffer, as before. V
thin film resistance between DSG and V
reach approximately 10 V. Then, the internal power-on cir-
cuitry opens G
tion shown in Figure 18. V
DAC output.
Loading the DAC and Using the CLR Input
When LDAC goes low, it closes G
ure 18. The voltage at V
the output of the DAC. The output stage remains connected in
this manner until a CLR signal is applied. Then the situation
reverts to that shown in Figure 17. Once again V
the same voltage as DSG until LDAC goes low. This recon-
nects the DAC output to the unity gain buffer.
DSG Voltage Range
During power-on, the V
connected to the relevant DSG pins via G
sistor, R. The DSG potential must obey the max ratings at all
times. Thus, the voltage at DSG must always be within the
range V
ages at the V
voltage applied to DSG should also be kept within the range
AGND – 2 V, AGND + 2 V.
Once the AD7834/AD7835 has powered on and the on-chip
amplifiers have settled, the situation is as shown as in Figure 17.
Any voltage that is now applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in nor-
mal operation. Thus, for specified operation, the maximum
voltage that can be applied to the DSG pin increases to the
maximum allowable V
that can be applied to DSG is the minimum V
the AD7834/AD7835 has fully powered on, the outputs can
track any DSG voltage within this minimum/maximum range.
POWER-ON OF THE AD7834/AD7835
Power should normally be applied to the AD7834/AD7835 in
the following sequence: first V
V
2 V of the relevant DSG potential during power-on, the
OUT
REF
5
(+) and V
has been disconnected from the DSG pin by the opening
but will track the voltage present at DSG via the unity
4
and G
SS
Figure 18. Output Stage with LDAC Low
DAC
– 0.3 V, V
OUT
2
6
is open, thus connecting the output of the DAC
3
REF
open, connecting the amplifier as a unity gain
and G
pins of the AD7834/AD7835 stay within
(–).
G
G
OUT
1
2
DD
DSG
REF
5
is connected to DSG via G
+ 0.3 V. However, in order that the volt-
and closes G
OUT
OUT
(+) voltage, and the minimum voltage
OUT
pins of the AD7834/AD7835 are
now follows the voltage present at
DD
is now at the same voltage as the
G
G
3
5
and V
AD7834/AD7835
1
and opens G
4
R
3
and G
SS
and G
OUT
G
G
, then V
6
4
6
and the thin film re-
) until V
REF
6
. This is the situa-
5
(–) voltage. After
will be closed
2
OUT
CC
5
as in Fig-
, then
and R (a
DD
V
remains at
OUT
and V
1
SS
is