CY7C1215F-133AC CYPRESS [Cypress Semiconductor], CY7C1215F-133AC Datasheet
CY7C1215F-133AC
Related parts for CY7C1215F-133AC
CY7C1215F-133AC Summary of contents
Page 1
... Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode Option Functional Description [1] The CY7C1215F SRAM integrates 32,768 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Logic Block Diagram A0, A1, A ADDRESS REGISTER ...
Page 2
... Document #: 38-05421 Rev 100-pin TQFP 15 16 CY7C1215F CY7C1215F 166 MHz 133 MHz 3.5 4.0 240 225 DDQ V 76 SSQ BYTE ...
Page 3
... CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a three-state condition. CY7C1215F , CE , and CE 1 ...
Page 4
... Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1215F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
Page 5
... Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1215F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. ...
Page 6
... ,BW ,BW ,BW ) and BWE = WRITE = H when all Byte Write Enable signals CY7C1215F DQ ADSC ADV Three-State Three-State Three-State Three-State Three-State X ...
Page 7
... CY7C1215F ...
Page 8
... Max, Device Deselected, All speeds DD ≥ V ≤ /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1215F Ambient Temperature V DD 0°C to +70°C 3.3V –5%/+10% Min. Max. 3.135 3.6 3.135 V DD 2.4 0.4 2 0.3V DD – ...
Page 9
... EIA/JESD51 Description T = 25° MHz 3.3V DDQ R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE CY7C1215F TQFP Package 41.83 9.99 Test Conditions = 3.3V ALL INPUT PULSES V DD 90% 10% GND ≤ (c) Page Unit °C/W °C/W Max. Unit ...
Page 10
... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1215F 166 MHz 133 MHz Min. Max Min. Max 1 1 6.0 7.5 2.5 3 ...
Page 11
... OEV OEHZ t OELZ t DOH Q(A2) Q( Q(A1) DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1215F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
Page 12
... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05421 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW . [ CY7C1215F ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 ...
Page 13
... Note: 19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 20 HIGH. Document #: 38-05421 Rev WES t WEH OELZ D(A3) t OEHZ Q(A2) Single WRITE DON’T CARE UNDEFINED CY7C1215F A5 D(A5) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ A6 D(A6) Back-to-Back WRITEs Page ...
Page 14
... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode. Ordering Information Speed (MHz) Ordering Code 166 CY7C1215F-166AC 133 CY7C1215F-133AC Document #: 38-05421 Rev. ** High-Z DON’T CARE Package Name Package Type A101 100-lead Thin Quad Flat Pack ...
Page 15
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1215F 51-85050-A ...
Page 16
... Document History Page Document Title: CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM Document Number: 38-05421 REV. ECN NO. Issue Date ** 200661 See ECN Document #: 38-05421 Rev. ** Orig. of Change NJY New Data Sheet CY7C1215F Description of Change Page ...