CY7C1215F-133AC CYPRESS [Cypress Semiconductor], CY7C1215F-133AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1215F-133AC
• Description: 1-Mb (32K x 32) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05421 Rev. **
Truth Table
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
6. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
Next Cycle
(BW
after the ADSP or with the assertion of ADSC . As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE
is a don't care for the remainder of the Write cycle
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) .
1
, CE
A
,BW
2
, and CE
B
,BW
[2, 3, 4, 5, 6, 7]
C
,BW
3
are available only in the TQFP package.
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
D
Add. Used
), BWE , GW = H .
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CE
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
3
CE
H
H
H
X
X
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
A
,BW
CE
H
X
X
H
H
X
X
H
H
X
H
X
H
X
H
X
L
L
L
L
L
L
L
B
,BW
1
C
,BW
ADSP
D
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
L
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
ADSC
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
ADV
H
H
H
H
[A:D]
X
X
X
X
X
X
X
H
H
H
H
X
H
H
X
L
L
L
L
. Writes may occur only on subsequent clocks
OE
X
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
Three-State X
Three-State X
Three-State X
Three-State X
Three-State X
Three-State X
Three-State Read
Three-State Read
DQ
Three-State Read
DQ
Three-State Read
DQ
Three-State Read
DQ
Three-State Write
Three-State Write
Three-State Write
Three-State Write
Three-State Write
Three-State Write
Three-State Write
Three-State X
CY7C1215F
DQ
Page 6 of 16
Read
Read
Read
Read
Write