PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 61

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.56
8.1.57
8.1.58
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER –
OFFSET 88h
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER
– OFFSET 8Ch
POWER MANAGEMENT ID REGISTER – OFFSET 90h
BIT
31:16
15:0
BIT
31:16
15:0
BIT
7:0
FUNCTION
Split Transaction
Commitment Limit
Split Transaction
Capability
FUNCTION
Split Transaction
Commitment Limit
Split Transaction
Capability
FUNCTION
Power Management ID
TYPE
TYPE
TYPE
RO
RW
RO
RW
RO
Page 61 of 77
DESCRIPTION
Split Transaction Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, causes the bridge to forward accepted split requests of any
size regardless of the amount of buffer space available. The limit can
be programmed at any time after reset. The value of the limit is equal
to the split transaction capacity field reset.
Reset to 0020h
Split Transaction Capability
The bridge returns 0020h to indicate that there are 32 ADQ’s (4K
bytes) available buffer space for storing split completions for
memory reads. This applies to requesters on the secondary bus
addressing completers on the primary bus.
Reset to 0020h
DESCRIPTION
Split Transaction Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, the bridge will forward accepted split requests of any size
regardless of the amount of buffer space available. The limit can be
programmed at any time after reset. The value of the limit is equal to
the split transaction capacity field reset.
Reset to 0020h
Split Transaction Capability
The bridge returns 0020h to indicate that there are 32 ADQ’s (4K
bytes) available buffer space for storing split completions for
memory reads. This applies to requesters on the secondary bus
addressing completers on the primary bus.
Reset to 0020h
DESCRIPTION
Power Management ID
Returns 01h when read indicating that this register set of the
capabilities list is a power management register set.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100