PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 66
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PI7C21P100NH
Manufacturer Part Number
PI7C21P100NH
Description
2-PORT PCI-X BRIDGE
Manufacturer
PERICOM [Pericom Semiconductor Corporation]
Datasheet
1.PI7C21P100NH.pdf
(77 pages)
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9.4
9.5
Table 9-1 JTAG BOUNDARY SCAN REGISTER
BOUNDARY SCAN REGISTER
The boundary scan register is a required set of serial-shiftable register cells, formed by
connecting boundary scan cells placed at the device’s signal pins into a shift register path. The
VDD, VSS, and JTAG pins are NOT in the boundary-scan chain. The input to the shift
register is TDI and the output from the shift register is TDO. There are 4 different types of
boundary scan cells, based on the function of each signal pin.
The boundary scan register cells are dedicated logic and do not have any system function.
Data may be loaded into the boundary-scan register master cells from the device input pins
and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions.
Parallel loading takes place on the rising edge of TCK.
JTAG BOUNDARY REGISTER ORDER
Register Number
Boundary Scan
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0
1
2
3
4
5
6
7
8
9
P_ACK64#
Pin Name
P_AD[10]
P_AD[11]
P_AD[12]
P_AD[13]
P_AD[14]
P_AD[15]
P_AD[16]
P_AD[17]
P_AD[18]
P_AD[19]
P_AD[20]
P_AD[21]
P_AD[22]
P_AD[23]
P_AD[24]
P_AD[25]
P_AD[26]
P_AD[27]
P_AD[28]
P_AD[29]
P_AD[30]
P_AD[31]
P_AD[0]
P_AD[1]
P_AD[2]
P_AD[3]
P_AD[4]
P_AD[5]
P_AD[6]
P_AD[7]
P_AD[8]
P_AD[9]
Page 66 of 77
Ball Location
M22
M21
A19
A20
C19
D18
G22
B20
G21
H22
H21
K22
D23
K21
K20
G23
B13
C13
B14
C15
B16
C16
B17
C17
F22
F20
E23
L22
L21
J22
J21
J23
A2
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
BIDIR
Type
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
Tri-state Control Cell
PI7C21P100
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