MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 20

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
COMMAND
COMMAND
ADDRESS
ADDRESS
NOTE: DQM is LOW.
CLK
CLK
DQ
DQ
BANK,
T0
COL n
T0
BANK,
COL n
READ
READ
CAS Latency = 2
CAS Latency = 3
T1
T1
NOP
NOP
Terminating a READ Burst
T2
T2
NOP
NOP
D
OUT
n
Figure 12
T3
T3
20
NOP
NOP
n + 1
D
D
OUT
OUT
n
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE com-
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element n + 3 is the last desired data ele-
ment of a longer burst.
TERMINATE
TERMINATE
Full-page READ bursts can be truncated with the
T4
BURST
T4
BURST
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 3
n + 2
D
D
OUT
OUT
512Mb: x4, x8, x16
T6
T6
NOP
NOP
n + 3
D
OUT
DON’T CARE
T7
NOP
©2000, Micron Technology, Inc.
SDRAM
ADVANCE