MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 39

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MT48LC128M4A2TG

Manufacturer Part Number
MT48LC128M4A2TG
Description
SYNCHRONOUS DRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
TIMING PARAMETERS
*CAS latency indicated in parentheses.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
A0-A9, A11, A12
SYMBOL*
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
DQML, DQMH
COMMAND
DQM /
BA0, BA1
A10
CKE
CLK
DQ
Precharge all
High-Z
t CKS
active banks
t CMS
t AS
SINGLE BANK
ALL BANKS
PRECHARGE
BANK(S)
T0
t AH
t CKH
t CMH
MIN
t CK
0.8
1.5
2.5
2.5
7.5
7
-7E
MAX
t RP
T1
NOP
MIN
0.8
1.5
2.5
2.5
7.5
10
-75
MAX
AUTO REFRESH MODE
T2
UNITS
REFRESH
AUTO
ns
ns
ns
ns
ns
ns
t CH
t RFC
39
NOP
(
(
(
(
(
(
(
)
(
)
(
)
(
)
)
)
)
)
)
(
(
(
)
(
)
(
)
)
(
(
(
(
(
(
)
)
(
(
)
(
)
(
)
)
(
)
)
)
)
)
)
(
(
(
)
(
)
(
(
)
)
SYMBOL*
t
t
t
t
t
t
)
)
)
CKH
CKS
CMH
CMS
RFC
RP
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CL
Tn + 1
REFRESH
AUTO
t
512Mb: x4, x8, x16
MIN
RFC
0.8
1.5
0.8
1.5
66
15
NOP
-7E
(
(
(
(
(
)
(
(
(
(
)
(
)
(
)
)
)
(
)
)
)
)
)
(
MAX
)
(
(
)
(
(
(
(
)
(
)
(
(
(
)
(
)
(
)
)
)
(
)
)
)
)
)
(
)
(
)
)
NOP
MIN
0.8
1.5
0.8
1.5
66
20
©2000, Micron Technology, Inc.
-75
To + 1
SDRAM
ADVANCE
ACTIVE
ROW
ROW
MAX
BANK
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns

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