MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 34
MT48LC128M4A2TG
Manufacturer Part Number
MT48LC128M4A2TG
Description
SYNCHRONOUS DRAM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT48LC128M4A2TG.pdf
(55 pages)
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AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35)
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
34
CL = 3
CL = 2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
t
t
ROH(3)
ROH(2)
t
t
t
t
t
t
t
CKED
t
t
DQM
DWD
t
t
t
t
MRD
DQD
DQZ
CCD
DAL
BDL
CDL
RDL
PED
DPL
512Mb: x4, x8, x16
-7E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-75
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
©2000, Micron Technology, Inc.
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SDRAM
ADVANCE
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
NOTES
15, 21
16, 21
16, 21
17
14
14
17
17
17
17
17
17
26
17
17
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