ICS650R01I ICST [Integrated Circuit Systems], ICS650R01I Datasheet - Page 2

• Manufacturer Part Number: ICS650R01I
• Description: System Peripheral Clock Source
• Manufacturer: ICST [Integrated Circuit Systems]

MDS 650-01B A
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• [phone]tel • [phone]fax
Pin Assignment
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
Pin Descriptions
BCLK2
PCLK4
BCLK1
Pin #
ACLK
GND
10
11
12
13
14
15
16
17
18
19
20
VDD
GND
1
2
3
4
5
6
8
9
BSEL
7
X2
X1
20 pin (150 mil) SSOP
14.318M
BCLK1
BCLK2
PCLK4
PCLK1
PCLK3
PCLK2
2
10
PSEL0
PSEL1
1
3
4
7
8
9
Name
ACLK
5
6
BSEL
VDD
GND
GND
GND
ASEL
VDD
OE
X2
X1
Type
16
15
14
13
12
11
17
XO
20
19
18
XI
O
O
O
O
O
O
O
O
P
P
P
P
P
I
I
I
I
I
14.31818 MHz buffered reference clock output.
PSEL1
PSEL0
PCLK2
PCLK3
VDD
GND
Description
BCLK1 and BCLK2 Select pin. Determines frequency of B clocks per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to ground.
Connect to ground.
BCLK1 output. Determined by BSEL pin per table above.
BCLK2 output. Determined by BSEL pin per table above. Only clock active if PSEL1, 0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
ASEL
14.318M
PCLK1
OE
2
Processor Clock (MHz)
B Clocks (MHz)
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
PSEL1 PSEL0
BSEL
M
M
M
M
0
1
0
0
0
1
1
1
System Peripheral Clock Source
BCLK1
3.688
50
80
M
M
M
0
1
0
1
0
1
Stops low all clo o cks except BCL L K2.
BCLK2
4.917
PCLK1
33.3334
TEST
TEST
25
40
25.00
40.00
20.00
20.00
20.00
Revision 041499
Audio Clock (MHz)
PCLK2,3
66.6667
33.3334
66.6667
ASEL
TEST
TEST
50.00
80.00
40.00
M
0
1
ICS650-01B
49.152
24.576
12.288
ACLK
Printed 11/15/00
PCLK4
TEST
TEST
25.00
25.00
18.75
20.00
25.00
25.00