CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing Diagrams
Write Cycle Timing
Notes:
14. WE is the combination of BWE, BWS
15. WDx stands for Write Data to Address X.
Data In
ADV
ADD
CE
CE
CE
CLK
ADSP
ADSC
GW
WE
OE
1
3
2
t
t
t
CES
ADS
CES
t
AS
High-Z
t
CES
WD1
t
ADVS
t
t
[14, 15]
t
Single Write
ADH
CEH
t
ADS
DS
ADV Must Be Inactive for ADSP Write
t
t
t
CYC
t
CEH
t
CEH
AH
WS
1a
1a
t
t
t
ADVH
t
WH
DH
ADH
[1:0]
WD2
, and GW to define a write cycle (see Write Cycle Descriptions table).
t
CH
= UNDEFINED
t
WS
t
CL
2a
t
WH
Burst Write
ADSP ignored with CE
2b
CE
1
10
masks ADSP
= DON’T CARE
2c
1
inactive
2d
ADSC initiated write
WD3
3a
Pipelined Write
Unselected with CE
High-Z
Unselected
2
CY7C1325