IS62C1024AL-35Q ISSI [Integrated Silicon Solution, Inc], IS62C1024AL-35Q Datasheet - Page 6

• Manufacturer Part Number: IS62C1024AL-35Q
• Description: 128K x 8 LOW POWER CMOS STATIC RAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS62C1024AL
IS65C1024AL
READ CYCLE NO. 2
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = V
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
4. Tested with OE HIGH.
6
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1a.
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
WC
AW
HA
SD
HD
HZWE
SCE
SCE
SA
PWE
LZWE
ADDRESS
1
2
(4)
(2)
(2)
DOUT
CE1
CE2
OE
Parameter
Write Cycle Time
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
(1,3)
t
ACE1/
t
t
HIGH-Z
LZCE1/
LZCE2
t
ACE2
t
AA
IL
Integrated Silicon Solution, Inc. — www.issi.com —
, CE2 = V
t
LZOE
t
DOE
t
RC
IH
.
(1,3)
Min.
35
25
25
25
25
20
—
0
0
0
3
(Over Operating Range, Standard and Low Power)
-35 ns
Max.
10
—
—
—
—
—
—
—
—
—
—
DATA VALID
Min.
t
45
35
35
35
35
25
—
HZCE
0
0
0
5
-45 ns
t
HZOE
Max.
t
15
—
—
—
—
—
—
—
—
—
—
OHA
ISSI
1-800-379-4774
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
01/24/05
Rev. C
®