IS63LV1024L ISSI [Integrated Silicon Solution, Inc], IS63LV1024L Datasheet - Page 7

• Manufacturer Part Number: IS63LV1024L
• Description: 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

AC WAVEFORMS
WRITE CYCLE NO. 1
IS63LV1024L
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
08/07/02
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
Symbol
t
t
t
t
t
t
t
t
t
t
t
output loading specified in Figure 1a.
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
WC
SCE
AW
HA
SA
PWE
PWE
SD
HD
HZWE
LZWE
ADDRESS
1
2
(1)
(2)
(2)
(2)
D
OUT
WE
D
CE
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to
Write End
Address Hold from
Write End
Address Setup Time
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
IN
(1,2
DATA UNDEFINED
t
(CE Controlled, OE = HIGH or LOW)
SA
t
HZWE
t
VALID ADDRESS
AW
1-800-379-4774
t
t
PWE1
PWE2
t
Min.
t
SCE
—
WC
8
7
8
0
0
7
8
5
0
3
(1,3)
-8 ns
HIGH-Z
(Over Operating Range)
Max.
—
—
—
—
—
—
—
—
—
—
4
t
SD
DATA
Min.
10
10
—
IN
7
8
0
0
7
5
0
3
-10 ns
VALID
Max.
—
—
—
—
—
—
—
—
—
—
5
t
HD
t
LZWE
t
HA
Min.
12
12
—
8
8
0
0
8
6
0
3
-12 ns
Max.
—
—
—
—
—
—
—
—
—
—
ISSI
6
CE_WR1.eps
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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