CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 23

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
Switching Waveforms
Read/Write Timing
Note:
46. Q(A
DATA Out (Q)
BWa#, BWb#
DATA In (D)
ADDRESS
BWa, BWb,
BWc, BWd
ADV/LD#
ADV/LD
1
) represents the first output from the external address A
CKE#
R/W#
CEN
WEN
CE
OE
CLK
CE#
OE#
[40, 43, 45, 46]
A
1
t
t
t
t
t
t
S
S
S
S
S
S
(continued)
BW(A
Read
A
2
t
KQ
2
)
t
t
t
t
t
t
H
H
H
H
H
H
Q(A
1
Write
)
A
t
3
KQHZ
1
t
. D(A
KC
t
KL
2
) represents the input data to the SRAM corresponding to address A
BW(A
Read
D(A
A
4
2
4
)
)
t
KQLZ
Q(A
3
BW(A
)
A
5
5
t
)
KH
Write
t
KQX
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
D(A
A
6
4
)
D(A
A
7
5
)
Read
Q(A
6
)
A
8
2
.
Page 23 of 31
Q(A
7
A
)
9