CY7C1354A CYPRESS [Cypress Semiconductor], CY7C1354A Datasheet - Page 25

• Manufacturer Part Number: CY7C1354A
• Description: 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05161 Rev. *B
Switching Waveforms
CE Timing
Notes:
48. Q(A
49. When either one of the Chip Enables (CE, CE
DATA Out (Q)
BWa#, BWb#
DATA In (D)
cycle after t
BWa, BWb,
BWc, BWd
ADDRESS
ADV/LD#
ADV/LD
1
) represents the first output from the external address A
CKE#
[40, 43, 45, 48, 49]
R/W#
CEN
WEN
CLK
OE#
CE#
OE
CE
A
1
t
OELZ
t
t
OEQ
t
S
t
S
t
S
KQLZ
(continued)
A
2
2
t
, or CE
S
t
t
t
H
H
H
Q(A
t
KQ
1
3
)
) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one
1
t
t
S
. D(A
t
S
KC
t
H
Q(A
t
KL
3
) represents the input data to the SRAM corresponding to address A
2
A
)
3
t
KQHZ
t
t
t
KQX
H
H
t
KH
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
t
D(A
SD
A
4
t
HD
3
)
Q(A
4
A
)
5
3
, etc.
Page 25 of 31
t
OEHZ