CY7C1361B CYPRESS [Cypress Semiconductor], CY7C1361B Datasheet - Page 28

• Manufacturer Part Number: CY7C1361B
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05302 Rev. *B
Timing Diagrams
Read/Write Cycle Timing
Notes:
23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC .
24. GW is HIGH.
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high-Z when exiting ZZ sleep mode.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
(continued)
Q(A1)
A2
t ADH
[21, 23, 24]
t CEH
t
t AH
CH
t CYC
t
CL
Q(A2)
t
OEHZ
A3
Single WRITE
t
t DS
WES
D(A3)
t DH
t
WEH
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
UNDEFINED
Q(A4+1)
BURST READ
Q(A4+2)
Q(A4+3)
CY7C1361B
CY7C1363B
D(A5)
A5
Back-to-Back
Page 28 of 34
WRITEs
D(A6)
A6