CY7C1380D CYPRESS [Cypress Semiconductor], CY7C1380D Datasheet - Page 12

• Manufacturer Part Number: CY7C1380D
• Description: 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05543 Rev. *A
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
TAP Timing
TAP AC Switching Characteristics
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes:
10. t
11. Test conditions are specified using the load in TAP AC test Conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
Over the Operating Range
t TMSS
t TDIS
PRELIMINARY
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
F
t
TL
= 1ns.
3
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CYC
[10, 11]
UNDEFINED
4
t TDOX
t TDOV
5
Min.
50
25
25
0
5
5
5
5
5
5
6
Max.
20
CY7C1380D
CY7C1382D
5
Page 12 of 29
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns