CY7C1381D CYPRESS [Cypress Semiconductor], CY7C1381D Datasheet - Page 23

• Manufacturer Part Number: CY7C1381D
• Description: 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05544 Rev. *A
Timing Diagrams
3
Notes:
23. Timing reference level is 1.5V when V
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Write Cycle Timing
Data Out (Q)
Data in (D)
ADDRESS
BWE,
BW
ADSP
ADSC
GW
ADV
CE
CLK
OE
X
BURST READ
High-Z
t ADS
t CES
t AS
[25, 26]
A1
(continued)
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
t
Single WRITE
CL
t
DS
D(A1)
t ADH
t
DH
DDQ
= 3.3V and is 1.25V when V
A2
D(A2)
DON’T CARE
PRELIMINARY
D(A2 + 1)
t
WES
BURST WRITE
t
WEH
DDQ
= 2.5V.
D(A2 + 1)
UNDEFINED
ADV suspends burst
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t ADVS
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
D(A3 + 2)
CY7C1381D
CY7C1383D
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