CY7C1381D CYPRESS [Cypress Semiconductor], CY7C1381D Datasheet - Page 24

• Manufacturer Part Number: CY7C1381D
• Description: 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05544 Rev. *A
Timing Diagrams
Read/Write Cycle Timing
Notes:
25. On this diagram, when CE is LOW: CE
26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC .
28. GW is HIGH.
Data Out (Q)
Data In (D)
BWE, BW
ADDRESS
ADSC
ADSP
ADV
CLK
OE
CE
X
A1
High-Z
t ADS
Back-to-Back READs
t CES
t AS
(continued)
Q(A1)
A2
t ADH
[25, 27, 28]
t CEH
t
t AH
CH
t CYC
t
CL
1
Q(A2)
is LOW, CE
t
OEHZ
A3
2
is HIGH and CE
Single WRITE
t
PRELIMINARY
t DS
WES
D(A3)
t DH
t
WEH
3
is LOW. When CE is HIGH: CE
DON’T CARE
A4
t OELZ
t CDV
Q(A4)
X
LOW.
UNDEFINED
Q(A4+1)
BURST READ
1
is HIGH or CE
Q(A4+2)
2
is LOW or CE
Q(A4+3)
CY7C1381D
CY7C1383D
3
D(A5)
is HIGH.
A5
Back-to-Back
Page 24 of 29
WRITEs
D(A6)
A6