CY7C1460AV25-167 CYPRESS [Cypress Semiconductor], CY7C1460AV25-167 Datasheet
CY7C1460AV25-167
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CY7C1460AV25-167 Summary of contents
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... TQFP and 165 fBGA packages CY7C1464AV25 available in 209-Ball fBGA package • IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram–CY7C1460AV25 (1 Mbit x 36) A0, A1, A REGISTER 0 MODE CLK ...
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... DQs DQP DQP DQP DQP DQP DQP f DQP g DQP h INPUT E E REGISTER 0 CY7C1460AV25-167 CY7C1462AV25-167 CY7C1464AV25-167 3.4 335 100 Page Unit ...
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... DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DDQ DQP 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... V b DDQ DDQ DDQ N DQP DDQ P NC NC/72M MODE A Document #: 38-05354 Rev. *A PRELIMINARY 165-Ball fBGA Pinout CY7C1460AV25 (1 Mbit × 36 CEN CLK ...
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... TDI Pin Description controls DQ a and DQP , BW controls and DQP , BW controls DQ and DQP CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 DQb DQb 3 A BWS DQb BWS DQb b f BWS DQb BWS DQb DQb ...
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... The outputs are automat controlled DQP controlled DQP is controlled DQP is controlled CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 and DQP , BW controls DQ and DQP controls DQ and DQP ...
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... On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d,e,f,g,h DQ /DQP a,b,c,d for CY7C1462AV25) (or a subset for byte write operations, see CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 /DQP for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b,c,d a,b /DQP for CY7C1464AV25, a,b,c,d,e,f,g,h for CY7C1460AV25 and DQ /DQP a,b,c,d a,b Page a,b a,b ...
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... Test Conditions ZZ > V − 0. > V − 0. < 0.2V This parameter is sampled This parameter is sampled CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 for CY7C1460AV25 and BW a,b,c,d a and CE , must remain inactive after the ZZ input returns LOW. ZZREC ) DD Second Third Fourth Address Address Address ...
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... Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) Sleep MODE Partial Write Cycle Description Function (CY7C1460AV25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – ...
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... DQP x x) Write All Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor- porates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 2.5V/1.8V I/O logic level. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...
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... Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Page ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE UNDEFINED CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 TDOV t TDOX Page ...
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... CH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. t Document #: 38-05354 Rev. *A PRELIMINARY [9, 10] Over the Operating Range Description / ns CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Min. Max. Unit MHz 25 ...
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... DDQ V = 1.8V DDQ GND ≤ V ≤ DDQ CY7C1462AV25 CY7C1464AV25 (1M ×36) (2M ×18) (512k ×72) 000 000 01011 01011 01011 001000 001000 001000 100111 010111 110111 00000110100 00000110100 1 1 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 .............................. 0. DDQ 0.9V 50Ω 50Ω 20pF O Min. Max. 1.7 2.1 1.6 0.4 0.2 0.2 1 0 0.3 DD –0.3 0.7 – ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document #: 38-05354 Rev. *A PRELIMINARY Bit Size (x36) Bit Size (x18 – – Description CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit Size (x72 – 138 Page ...
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... Boundary Scan Order CY7C1460AV25 (1 Mbit x 36) Bit# Ball ID Bit N10 44 4 P11 P10 50 10 R10 51 11 R11 52 12 H11 53 13 N11 54 14 M11 55 15 L11 56 16 K11 57 17 J11 ...
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... J10 75 H11 76 H10 77 G11 78 G10 79 F11 80 F10 81 E10 82 E11 83 D11 84 D10 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [12] (continued) Bit# Ball Internal Bit# Ball ID ...
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... CY7C1464AV25 (512K x 72) Ball ID Bit# Ball 100 B7 101 A7 102 103 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Bit# Ball ID D1 128 T6 E1 129 U3 E2 130 V3 F2 131 T4 F1 132 T5 G1 133 U4 G2 134 V4 H2 135 ...
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... /2), undershoot: V (AC)> -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Ambient Temperature DDQ 0°C to +70°C 2.5V–5%/+5% 1. Min. Max. 2.375 2.625 2.375 ...
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... Min. Max. 1 4.0 250 1.5 1.5 2.6 2.6 1.0 2.6 and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ = 1.8V. DDQ CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 165 FBGA 209 FBGA 20.8 25.31 3.2 4.48 165 FBGA 209 FBGA 6 5 ALL INPUT PULSES 90% ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 200 167 Min. Max. Min. Max. 1.3 1.5 3.0 3 1.4 1.5 1.4 1.5 1.4 1.5 1.4 1.5 1.4 1.5 1.4 1.5 0.4 0.5 0.4 0.5 0.4 0.5 0.4 0.5 0.4 0.5 0.4 0 ...
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... ALL INPUTS (except ZZ) Outputs (Q) Document #: 38-05354 Rev. *A PRELIMINARY [23,24,25 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE High-Z DON’T CARE CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI DESELECT or READ Only Page ...
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... CY7C1460AV25-167AXC CY7C1462AV25-167AXC CY7C1460AV25-167BZC CY7C1462AV25-167BZC CY7C1464AV25-167BGC CY7C1460AV25-167BZXC CY7C1462AV25-167BZXC CY7C1464AV25-167BGXC Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts Notes: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle 27 ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05354 Rev. *A PRELIMINARY CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 51-85050-*A Page ...
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... SEATING PLANE C Document #: 38-05354 Rev. *A PRELIMINARY 165-Ball FBGA ( 1.40 mm) BB165C CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY 209-Ball FBGA ( 1.76 mm) BB209A CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 51-85167-** ...
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... Document History Page Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05354 Orig. of REV. ECN No. Issue Date Change ** 254911 See ECN SYT *A 303533 See ECN SYT Document #: 38-05354 Rev. *A PRELIMINARY Description of Change New data sheet Part number changed from previous revision (ew and old part number differ by the letter " ...