AD9520-5 AD [Analog Devices], AD9520-5 Datasheet - Page 58
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AD9520-5
Manufacturer Part Number
AD9520-5
Description
12 LVPECL/24 CMOS Output Clock Generator
Manufacturer
AD [Analog Devices]
Datasheet
1.AD9520-5.pdf
(80 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9520-5BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
AD9520-5
Addr
(Hex)
193
194
195
196
197
198
199
19A
19B
19C
to
1DF
VCO Divider and CLK Input
1E0
1E1
1E2
to
22A
System
230
231
Update All Registers
232
233
to
9FF
EEPROM Buffer Segment
A00
A01
A02
A03
Parameter
Divider 1
(PECL)
Divider 2
(PECL)
Divider 3
(PECL)
VCO divider
Input CLKs
Power-down
and SYNC
IO_UPDATE
EEPROM
Buffer
Segment
Register 1
EEPROM
Buffer
Segment
Register 2
EEPROM
Buffer
Segment
Register 3
EEPROM
Buffer
Segment
Register 4
Bit 7 (MSB)
Divider 1
bypass
Divider 2
bypass
Divider 3
bypass
Unused
0
0
EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)
EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)
Bit 6
Divider 1 low cycles
Divider 2 low cycles
Divider 3 low cycles
Divider 3
ignore
SYNC
Divider 1
ignore
SYNC
Divider 2
ignore
SYNC
(default = 01b)
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Bit 5
Divider 1
force
high
Divider 2
force
high
Divider 3
force
high
EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)
EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)
Rev. 0 | Page 58 of 80
Bit 4
Divider 1
start high
Divider 2
start high
Divider 3
start high
Power -
down
clock
input
section
Unused
Unused
Unused
Unused
Bit 3
Unused
Unused
Disable
power-on
SYNC
Unused
Unused
Bit 2
Channel 1
Channel 2
Channel 3
power-
down
Power-
down
SYNC
power-
power-
Reserved
down
down
Divider 1 high cycles
Divider 2 high cycles
Divider 3 high cycles
phase offset
phase offset
phase offset
Divider 1
Divider 2
Divider 3
Unused
Bit 1
Channel 3
direct-to-
output
Power-
down
distribution
reference
Channel 1
Channel 2
direct-to-
direct-to-
VCO divider
output
output
Bit 0 (LSB)
Disable
Divider 3
DCC
Bypass
VCO
divider
Soft
SYNC
IO_UPDATE
(self-clearing)
Divider 1
Divider 2
Disable
Disable
DCC
DCC
Default
Value
(Hex)
33
00
00
11
00
00
00
00
00
00
00
20
00
00
00
00
00
00
00
02
00