CAT28F001 CATALYST [Catalyst Semiconductor], CAT28F001 Datasheet - Page 10

• Manufacturer Part Number: CAT28F001
• Description: 1 Megabit CMOS Boot Block Flash Memory
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT28F001
When the Status Register indicates that programming is
complete, the Program Status bit should be checked. If
program error is detected, the Status Register should be
cleared. The internal WSM verify only detects errors for
“1s” that do not successfully program to “0s”. The
Command Register remains in Read Status Register
mode until further commands are issued to it.
If erase/byte program is attempted while V
Status bit (SR.5/SR.4) will be set to “1”. Erase/Program
attempts while V
results and should not be attempted.
EMBEDDED ALGORITHMS
The CAT28F001 integrates the Quick Pulse program-
ming algorithm on-chip, using the Command Register,
Status Register and Write State Machine (WSM). On-
chip integration dramatically simplifies system software
and provides processor-like interface timings to the
Command and Status Registers. WSM operation, inter-
nal program verify, and V
monitored and reported via appropriate Status Register
bits. Figure 4 shows a system software flowchart for
device programming.
As above, the Quick Erase algorithm is now imple-
mented internally, including all preconditioning of block
data. WSM operation, erase verify and V
presence are monitored and reported through the Status
Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup has
been written, both the Erase Status and Program Status
Doc. No. 25071-00 2/98 F-1
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE STATUS
SR.4 = PROGRAM STATUS
SR.3 = VPP STATUS
SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase in Progress/Completed
1 = Error in Block Erasure
0 = Successful Block Erase
1 = Error in Byte Program
0 = Successful Byte Program
1 = V
0 = V
out when polling the Status Register.
PP
PP
Low Detect; Operation Abort
Okay
WSMS
PPL
7
< V
PP
PP
ESS
high voltage presence are
< V
6
PPH
produce spurious
ES
PP
5
PP
high voltage
= V
PPL
PS
, the
4
10
VPPS
NOTES:
The Write State Machine Status Bit must first be checked to
If the Program AND Erase Status bits are set to “1s” during an
If V
The V
bits will be set to “1”. When issuing the Erase Setup and
Erase Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 5 shows a system software flowchart for
block erase.
The entire sequence is performed with V
Abort occurs when RP transitions to V
V
programmed or Block data is partially erased at the
location where it was aborted. Block erasure or a repeat
of byte programming will initialize this data to a known
value.
BOOT BLOCK PROGRAM AND ERASE
The boot block is intended to contain secure code which
will minimally bring up a system and control program-
ming and erase of other blocks of the device, if needed.
Therefore, additional “lockout” protection is provided to
guarantee data integrity. Boot block program and erase
operations are enabled through high voltage V
either RP or OE, and the normal program and erase
command sequences are used. Reference the AC
Waveforms for Program/Erase.
If boot block program or erase is attempted while RP is
at V
be set to “1”, reflective of the operation being attempted
and indicating boot block lock. Program/erase attempts
while V
should not be attempted.
PPL
3
PP
determine program or erase completion, before the
Program or Erase Status bits are checked for success.
erase attempt, an improper command sequence was
entered. Attempt the operation again.
cleared before another program or erase operation is
attempted.
continuous indication of V
the V
sequences have been entered and informs the system if
V
guaranteed to report accurate feedback between V
V
IH
PP
PPH
. Although the WSM is halted, byte data is partially
PP
low status is detected, the Status Register must be
, either the Program Status or Erase Status bit will
has not been switched on. The V
Status bit, unlike an A/D converter, does not provide
PP
.
IH
level only after the program or erase command
< RP < V
R
2
HH
R
1
PP
produce spurious results and
level. The WSM interrogates
PP
R
0
Status bit is not
IL
, or V
PP
PP
PPL
at V
drops to
and
HH
PPH
on
.