CY7C429 CYPRESS [Cypress Semiconductor], CY7C429 Datasheet - Page 12

• Manufacturer Part Number: CY7C429
• Description: 64K/128K x 9 Deep Sync FIFOs
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06007 Rev. *B
Switching Waveforms
Notes:
20. t
21. PAE offset = n.
22. If a read is preformed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW.
Full Flag Timing
Programmable Almost Empty Flag Timing
(if applicable)
(if applicable)
RCLK is less than t
WEN2
SKEW2
WEN2
Q
D
WCLK
WEN1
REN1,
WCLK
RCLK
WEN1
REN1,
REN2
RCLK
0
0
REN2
PAE
–D
–Q
OE
FF
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
8
8
DATA IN OUTPUT REGISTER
t
t
LOW
SKEW2
SKEW1
CLKH
, then PAE may not change state until the next RCLK.
[ 13 ]
t
ENS
NO WRITE
(continued)
t
SKEW2
t
WFF
t
t
A
ENH
t
t
ENS
ENS
[ 20 ]
t
t
ENH
ENH
t
CLKL
t
DS
Note 21
t
PAE
DATA WRITE
DATA READ
t
ENS
t
WFF
t
SKEW1
N + 1 WORDS
t
ENS
[ 13 ]
IN FIFO
t
ENS
NO WRITE
t
ENH
t
WFF
t
t
A
ENH
Note 22
CY7C4281
CY7C4291
NEXT DATA READ
Page 12 of 16
DATA WRITE
t
PAE