CY7C65632-28LTXC CYPRESS [Cypress Semiconductor], CY7C65632-28LTXC Datasheet

CY7C65632-28LTXC

Manufacturer Part Number

CY7C65632-28LTXC

Description

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY7C65632-28LTXC.pdf (25 pages)

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HX2VL™ Very Low Power USB 2.0 Hub Controller

Features

■

Cypress Semiconductor Corporation

Document Number: 001-67568 Rev. *F

Block Diagram – CY7C6563X

High performance, low-power USB 2.0 Hub, optimized for low

cost designs with minimum Bill-of-material

USB 2.0 hub controller

❐

Very low power consumption

❐

Highly integrated solution for reduced BOM cost

❐

Compliant with USB 2.0 specification

Up to four downstream ports support

Downstream ports are backward compatible with FS, LS

Single transaction translator (TT) for low cost

Supports bus-powered and self-powered modes

Auto switching between bus-powered and self-powered

Single MCU with 2K ROM and 64 byte RAM

Lowest power consumption

Internal regulator – single power supply 5 V required

Provision of connecting 3.3 V with external regulator

Integrated upstream pull-up resistor

Integrated pull-down resistors for all downstream ports

Integrated upstream/downstream termination resistors

12/27/48

OSC-in

Crystal

OR 12

MHz

USB Downstream Port 1

USB 2.0

D+ D-

PHY

Hub Repeater

USB Upstream Port

PLL

USB 2.0 PHY

D+

Control

Port

LED

D-

USB Downstream Port 2

USB 2.0

D+ D-

PHY

•

Interface

Engine

Serial

Control

Port

198 Champion Court

LED

Routing Logic

Transaction Translator

USB Downstream Port 3

USB 2.0

D+ D-

PHY

HX2VL™ Very Low Power USB 2.0

Control Logic

HS USB

Control

■

Port

❐

Downstream port management

❐

Maximum configurability

❐

Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin

(5 × 5 mm) QFN packages

Supports 0 °C to 70 °C temperature range

LED

Integrated port status indicator control

12 MHz +/– 500 ppm external crystal with drive level 600 µW

(integrated PLL) clock input with optional 27/48 MHz

oscillator clock input

Internal power failure detection for ESD recovery

Support individual and ganged mode power management

Overcurrent detection

Two port status indicators per downstream port

Slew rate control for EMI management

VID and PID are configurable through external EEPROM

Number of ports, removable/non-removable ports are

configurable through EEPROM and I/O pin configuration

I/O pins can configure gang/individual mode power

switching, reference clock source and polarity of power

switch enable pin

Configuration options also available through mask ROM

•

1.8V

3.3V

USB Downstream Port 4

USB 2.0

D+ D-

San Jose

PHY

RAM

MCU

Regulator

ROM

Control

CY7C65632, CY7C65634

Port

CA 95134-1709

LED

3.3V i/p (with ext. reg. & 28 QFN)

NC (with ext. reg. & 48 TQFP)

3.3V o/p (for int. reg.)

For two port version, USB Downstream

ports 3 and 4 are to be No connect from

the Chip I/O perspective.

5V i/p (for internal regulator)

NC (for external regulator)

Hub Controller

I2C /

SPI

Revised July 2, 2012

•

408-943-2600

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