CAT93C66 CATALYST [Catalyst Semiconductor], CAT93C66 Datasheet - Page 6

• Manufacturer Part Number: CAT93C66
• Description: 4-Kb Microwire Serial CMOS EEPROM
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT93C66
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
For the CAT93C66, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
address space, then loops back to address 0. In the
Figure 1. Sychronous Data Timing
Figure 2. READ Instruction Timing
Doc. No. 1089 Rev. P
DO
CS
SK
DI
DO
SK
CS
DI
1
t CSS
1
0
HIGH-Z
A N
VALID
t DIS
A N–1
t SKHI
PD0
Dummy 0
or t
t
PD0
PD1
).
A 0
t DIS
t SKLOW
6
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Erase/Write Enable and Disable
The CAT93C66 powers up in the write disable state. Any
writing after power-up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can
be read normally from the device regardless of the write
enable/disable
instructions timing is shown in Figure 3.
D 15 . . . D 0
or
D 7 . . . D 0
VALID
Address + 1
D 15 . . . D 0
or
D 7 . . . D 0
enable)
t DIH
t PD0, t PD1
Don't Care
DATA VALID
status.
Address + 2
D 15 . . . D 0
or
D 7 . . . D 0
instruction.
The
Characteristics subject to change without notice
t CSH
EWEN
© 2007 Catalyst Semiconductor, Inc.
Address + n
D 15 . . .
or
D 7 . . .
t CSMIN
Once
and
the
EWDS
write