CY7C68033 CYPRESS [Cypress Semiconductor], CY7C68033 Datasheet - Page 16
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CY7C68033
Manufacturer Part Number
CY7C68033
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C68033.pdf
(33 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68033-56BAXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C68033-56LTXC
Manufacturer:
Cypress
Quantity:
270
Document #: 001-04247 Rev. *D
Table 8. NX2LP-Flex Pin Descriptions (continued)
Port B
Number
56 QFN
PORT D
Pin
39
40
18
19
20
21
22
23
24
25
45
Default Pin
PA6 or
PKTEND
PA7 or
FLAGD or
SLCS#
PB0 or
FD[0]
PB1 or
FD[1]
PB2 or
FD[2]
PB3 or
FD[3]
PB4 or
FD[4]
PB5 or
FD[5]
PB6 or
FD[6]
PB7 or
FD[7]
PD0 or
FD[8]
Name
Firmware
GPIO0
GPIO1
NAND
Usage
(Input)
(Input)
CE0#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
Default
(PD0)
(PA6)
(PA7)
(PB0)
(PB1)
(PB2)
(PB3)
(PB4)
(PB5)
(PB6)
(PB7)
State
[6]
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the
endpoint and whose polarity is programmable via FIFOPIN-
POLAR[5].
GPIO1 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and PORTACFG[7] bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
GPIO0 is a general purpose I/O signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
DD0 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
DD1 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
DD2 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
DD3 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
DD4 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
DD5 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
DD6 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
DD7 is a bidirectional NAND data bus signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
CE0# is a NAND chip enable output signal.
CY7C68033/CY7C68034
Description
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