CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 11

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-2. ATACB2 Field Descriptions
Document 38-08030 Rev. *H
Byte
6-15
4
5
bATACB2TransferBlockCount[7:4] These bits indicate the DRQ block size in 512-byte increments. This value is log
bmATACB2ActionSelect2[3:0]
bATACB2DeviceHeadData
bATACB2TaskFileWriteData
Field Name
This field controls the execution of the ATACB according to the bitfield values:
These bytes contain ATA register data used with ATA command or PIO write
Bit 1 DeviceSelectionOverride - This bit determines when the device selection
will be performed in relation to the command register write accesses.
0 = Device selection will be performed prior to command register accesses
1 = Device selection will be performed following command register accesses
Bit 0 TaskFileRead - This bit determines whether or not the taskfile register data
selected in bmATACB2RegisterSelect is returned. If this bit is set, the
dCBWDataTransferLength field must be set to 12.
0 = Execute ATACB2 command and data transfer (if any)
1 = Only read taskfile registers selected in bmATACBRegisterSelect and return
0x00h for all others. The format of the 12 bytes of returned data is as follows:
base 2 of the block size. Legal values are 0 (1 sector per block) through 8 (256
sectors per block). A command failed status will be returned if an illegal value
is used in the ATACB2. For commands using multiple sector PIO data transfers,
the number of sectors per block must equal the current Multiple Sector Setting
of the drive. These bits should be set to ‘0’ for non-multiple, non-UDMA
commands.
Bits 3-1 Reserved - These bits must be set to ‘0’
Bit 0 48-bit-write - Determines whether or not M data is used to read 1F2-1F5
0 = Do not read or write 1F2-1F5 with “-M” data
1 = Read or write 1F2-1F5 with “-M” data
The contents of this field are used for writing the Device Head register when
Byte 2, Bit 6 of the ATACB2 is set to ‘1’. Otherwise, the value written will be
determined by the bridge.
Bits 7-5 DevHead - Data used to write to Device Head register.
Bit 4 DEVOverride - This bit reflects the state of Byte 3, Bit 5 of the ATACB2.
Bits 3-0 DevHead - Data used to write to Device head register.
operations. Only registers selected in bmATACB2RegisterSelect are required
to hold valid data when accessed. The registers are as follows:
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Address offset 0x00h (3F6h) Alternate Status (HOB=0)
Address offset 0x01h (1F6h) Device / Head (HOB=0)
Address offset 0x02h (1F1h) Error (HOB=0)
Address offset 0x03h (1F2h-M) Sector Count (HOB=1)
Address offset 0x04h (1F3h-M) LBA Low (Sector Number) (HOB=1)
Address offset 0x05h (1F4h-M) LBA Mid (Cylinder Low) (HOB=1)
Address offset 0x06h (1F5h-M) LBA High (Cylinder High) (HOB=1)
Address offset 0x07h (1F2h-L) Sector Count (HOB=0)
Address offset 0x08h (1F3h-L) LBA Low (HOB=0)
Address offset 0x09h (1F4h-L) LBA Mid (HOB=0)
Address offset 0x0Ah (1F5h-L) LBA High (HOB=0)
Address offset 0x0Bh (1F7h) Status (HOB=0)
ATACB2 Address offset 6h (1F1h) Features
ATACB2 Address offset 7h (1F2h-M) Sector Count
ATACB2 Address offset 8h (1F3h-M) LBA Low (Sector Number)
ATACB2 Address offset 9h(1F4h-M) LBA Mid (Cylinder Low)
ATACB2 Address offset Ah (1F5h-M) LBA High (Cylinder High)
ATACB2 Address offset Bh (1F2h-L) Sector Count
ATACB2 Address offset Ch (1F3h-L) LBA Low
ATACB2 Address offset Dh (1F4h-L) LBA Mid
ATACB2 Address offset Eh (1F5h-L) LBA High
ATACB2 Address offset Fh (1F7h) Command
Field Description
CY7C68310
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