CY7C68310 CYPRESS [Cypress Semiconductor], CY7C68310 Datasheet - Page 17

• Manufacturer Part Number: CY7C68310
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 6-2. EEPROM Organization (continued)
Document 38-08030 Rev. *H
0x0C
Address
I
2
C
ATA Read Kludge
IMODE
SYSIRQ
DISKRDY
ATA Translation Enable
ATA UDMA Enable
ATAPI UDMA Enable
ROM UDMA Mode
Field Name
Enable for the DRVPWRVLD pin. DRVPWRVLD is typically
only be enabled in applications where the CY7C68310 is
VBUS powered.
‘0’ = pin disabled (most systems)
‘1’ = pin enabled
Bit(1)
PIO data read high-Z control. Enabling this will high-Z the
ATA data bus during PIO read operations while addressing
the data register. In most applications this bit is set to ‘0.’
‘0’ = Normal operation as per ATA/ATAPI interface specifi-
cation
‘1’ = High-Z DD[15:0] during PIO data register reads
Bit (0) – Read only
This bit reflects the state of the IMODE input pin at start-up.
Bits(7) – Read only
This bit reflects the current logic state of the SYSIRQ input.
Bit(6) – Read only
This bit reflects the current logic state of the DISKRDY input.
Bit(5)
Enable ATAPI to ATA protocol translation enable. If enabled,
AND if an ATA device is detected, ATA translation is enabled.
If Skip ATA/ATAPI Device Initialization is set ‘1,’ Force ATA
Device must also be set ‘1’ in order to utilize ATA translation.
‘0’ = ATA Translation Disabled
‘1’ = ATA Translation Enable
Bit(4)
Enable Ultra Mode data transfer support for ATA devices. If
enabled, AND the ATA device reports UDMA support, the
CY7C68310 will utilize UDMA data transfers.
‘0’ = Disable ATA device UDMA support
‘1’ = Enable ATA device UDMA support
Bit(3)
Enable Ultra Mode data transfer support for ATAPI devices.
If enabled, AND the ATAPI device reports UDMA support,
the CY7C68310 will utilize UDMA data transfers.
‘0’ = Disable ATAPI device UDMA support
‘1’ = Enable ATAPI device UDMA support
Bits(2:0)
ROM UDMA Mode indicates the highest UDMA mode
supported by the product. The CY7C68310 will utilize the
lesser of ROM UDMA Mode and the highest mode
supported by the device. UDMA read operation mode timing
is controlled by the device.
mode 0
mode 1
mode 2
mode 3
mode 4
000
001
010
011
100
66.7 ns per 16-bit word write
133.3 ns per 16-bit word write
100 ns per 16-bit word write
66.7 ns per 16-bit word write
33.3 ns per 16-bit word write
Field Description
Required
I
2
C Data
CY7C68310
Page 17 of 34
Example
I
2
C Data
0x3C