AD2S80ASE AD [Analog Devices], AD2S80ASE Datasheet - Page 2

• Manufacturer Part Number: AD2S80ASE
• Description: Variable Resolution, Monolithic Resolver-to-Digital Converter
• Manufacturer: AD [Analog Devices]

AD2S80A–SPECIFICATIONS
Parameter
SIGNAL INPUTS
REFERENCE INPUT
CONTROL DYNAMICS
ACCURACY
VELOCITY SIGNAL
INPUT/OUTPUT PROTECTION
DIGITAL POSITION
INHIBIT
ENABLE
BYTE SELECT
SHORT CYCLE INPUTS
Frequency
Voltage Level
Input Bias Current
Input Impedance
Maximum Voltage
Frequency
Voltage Level
Input Bias Current
Input Impedance
Repeatability
Allowable Phase Shift
Tracking Rate
Bandwidth
Angular Accuracy
Monotonicity
Missing Codes (16-Bit Resolution)
Linearity
Reversion Error
DC Zero Offset
DC Zero Offset Tempco
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
Output Load
Analog Inputs
Analog Outputs
Resolution
Output Format
Load
Sense
Time to Stable Data
ENABLE Time
Sense
LOGIC LO
Time to Data Available
SC1 SC2
0
0
1
1
3
3
0
1
0
1
1
3
2
Conditions
(Signals to Reference)
10 Bits
12 Bits
14 Bits
16 Bits
User Selectable
A, J, S
B, K, T
L, U
Guaranteed Monotonic
A, B, J, K, S, T
L, U
Over Full Range
1 mA Load
Mean Value
Overvoltage Protection
Short Circuit O/P Protection
10, 12, 14, and 16
Bidirectional Natural Binary
Logic LO to Inhibit
Logic LO Enables Position
Output. Logic HI Outputs in
High Impedance State
MS Byte DB1–DB8,
LS Byte DB1–DB8,
Internally Pulled High
(100 k ) to +V
10 Bit
12 Bit
14 Bit
16 Bit
LS Byte DB9–DB16
LS Byte DB9–DB16
(typical at +25 C unless otherwise noted)
S
–2–
Min
50
1.8
1.0
50
1.0
1.0
–10
35
60
8
5.6
AD2S80A
Typ
2.0
60
60
–22
1
1
9
8
8
Max
20,000
2.2
150
8
20,000
8.0
150
1
+10
1040
260
65
16.25
4
1
6
1.5
1.0
3
600
110
140
2
10
10.5
10.4
4 +1 LSB
2 +1 LSB
8 +1 LSB
3
Units
Hz
V rms
nA
M
V pk
Hz
V pk
nA
M
LSB
Degrees
rps
rps
rps
rps
arc min
arc min
arc min
Codes
Code
% FSD
% FSD
mV
% FSD
V
% rms O/P
k
V
mA
LSTTL
ns
ns
ns
V/ C
REV. A