PCF8594C-2P ICST [Integrated Circuit Systems], PCF8594C-2P Datasheet - Page 12

• Manufacturer Part Number: PCF8594C-2P
• Manufacturer: ICST [Integrated Circuit Systems]

Philips Semiconductors
11 I
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
V
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
1997 Feb 13
SDA input/output (pin 5)
V
V
V
I
C
Data retention time
t
f
t
t
t
t
t
t
t
t
t
t
SYMBOL
LO
S
IH
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
SYMBOL
IL
IH
OL
256 to 1024
I
I
2
with an input voltage swing from V
internally provided by a transmitter.
C-bus interface
2
C-BUS CHARACTERISTICS
LOW level input voltage
HIGH level input voltage
LOW level output voltage
output leakage current
input capacitance
data retention time
clock frequency
bus free time between a STOP and START
condition
START condition hold time after which first clock
pulse is generated
LOW level clock period
HIGH level clock period
set-up time for STARt condition
data hold time
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
for bus compatible masters
for bus devices
8-bit CMOS EEPROMs with
PARAMETER
PARAMETER
SS
to V
DD
; see Fig.10.
I
V
V
T
12
OL
amb
OH
I
= V
= 3 mA; V
= V
= 55 C
CONDITIONS
SS
DD
repeated start
note 1
CONDITIONS
DD(min)
0.7V
10
0.8
0
4.7
4.0
4.7
4.0
4.7
5
0
250
4.0
PCF85xxC-2 family
MIN.
MIN.
DD
0.3V
+6.5
0.4
1
7
100
1
300
Product specification
MAX.
MAX.
DD
V
V
V
pF
years
kHz
ns
ns
ns
A
s
s
s
s
s
s
s
s
UNIT
UNIT
IL
and