PCF8594C-2P ICST [Integrated Circuit Systems], PCF8594C-2P Datasheet - Page 8

• Manufacturer Part Number: PCF8594C-2P
• Manufacturer: ICST [Integrated Circuit Systems]

Philips Semiconductors
8.3
Following a START condition the bus master must output
the address of the slave it is accessing. The 4 MSBs of the
slave address are the device type identifier (see Fig.5).
For the PCF85xxC-2 this is fixed to ‘1010’.
The next three significant bits address a particular device
or memory page (page = 256 bytes of memory). A system
could have up to eight PCF8582C-2 (or four PCF8594C-2
containing two memory pages each or two PCF8598C-2
containing four memory pages each, respectively) devices
on the bus. The eight addresses are defined by the state
of the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to
be performed. When set to logic 1 a read operation is
selected.
Address bits must be connected to either V
8.4
8.4.1
For a write operation the PCF85xxC-2 requires a second
address field. This address field is a word address
providing access to the 256 words of memory. Upon
receipt of the word address the PCF85xxC-2 responds
with an acknowledge and awaits the next eight bits of data,
again responding with an acknowledge. Word address is
automatically incremented. The master can now terminate
the transfer by generating a STOP condition or transmit up
to six more bytes of data and then terminate by generating
a STOP condition.
1997 Feb 13
handbook, halfpage
256 to 1024
I
2
C-bus interface
Device addressing
Write operations
B
YTE
/
1
WORD WRITE
Fig.5 Slave address.
0
1
8-bit CMOS EEPROMs with
0
A2
A1
A0 R/W
MBC793
DD
or V
SS
.
8
After this STOP condition the E/W cycle starts and the bus
is free for another transmission. Its duration is 10 ms per
byte.
During the E/W cycle the slave receiver does not send an
acknowledge bit if addressed via the I
8.4.2
The PCF85xxC-2 is capable of an eight-byte page write
operation. It is initiated in the same manner as the byte
write operation. The master can transmit eight data bytes
within one transmission. After receipt of each byte the
PCF85xxC-2 will respond with an acknowledge.
The typical E/W time in this mode is 9
Erasing a block of 8 bytes in page mode takes typical
3.5 ms and sequential writing of these 8 bytes another
typical 28 ms.
After the receipt of each data byte the three low order bits
of the word address are internally incremented. The high
order five bits of the address remain unchanged. The slave
acknowledges the reception of each data byte with an
ACK. The I
master after the 8th byte with a STOP condition. If the
master transmits more than eight bytes prior to generating
the STOP condition, no acknowledge will be given on the
ninth (and following) data bytes and the whole
transmission will be ignored and no programming will be
done. As in the byte write operation, all inputs are disabled
until completion of the internal write cycles.
8.4.3
A write to the EEPROM is always performed if the pin WP
is LOW (not on PCF8582C-2). If WP is HIGH, then the
upper half of the EEPROM is write-protected and no
acknowledge will be given by the PCF85xxC-2 when one
of the upper 256 EEPROM bytes (PCF8594C-2) or
512 EEPROM bytes (PCF8598C-2) is addressed.
However, an acknowledge will be given after the slave
address and the word address.
P
R
AGE WRITE
EMARK
2
C-bus data transfer is terminated by the
PCF85xxC-2 family
Product specification
2
C-bus.
3.5 ms = 31.5 ms.