M41ST85WMX6E STMICROELECTRONICS [STMicroelectronics], M41ST85WMX6E Datasheet
M41ST85WMX6E
Related parts for M41ST85WMX6E
M41ST85WMX6E Summary of contents
Page 1
I KEY FEATURES AUTOMATIC BATTERY SWITCHOVER and WRITE PROTECT FOR: – Internal Serial RTC and – External low power SRAM (LPSRAM) 2 400kHz I C SERIAL INTERFACE 3.0/3.3V OPERATING VOLTAGE – 2.7 to 3.6V CC ULTRA-LOW BATTERY ...
Page 2
M41ST85W TABLE OF CONTENTS KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
M41ST85W SUMMARY DESCRIPTION The M41ST85W is a combination Serial Real- Time Clock, Microprocessor Supervisor, and NVRAM Supervisor built in a low power CMOS SRAM process and has a 64-byte memory space with 44 bytes of NVRAM and 20 ...
Page 5
Figure 3. Logic Diagram V BAT ( SCL SDA EX M41ST85W RSTIN1 RSTIN2 WDI PFI V SS Note: 1. For 28-pin, 300mil embedded crystal SOIC only. Figure 4. 28-pin SOIC Connections SQW ...
Page 6
M41ST85W Figure 6. Block Diagram SDA INTERFACE SCL (2) 32KHz Crystal OSCILLATOR WDI BAT RSTIN1 RSTIN2 EX PFI 1.25V (Internal) Note: 1. Open drain output 2. Crystal integrated into SOIC package for MX package option. 6/34 REAL ...
Page 7
Figure 7. Hardware Hookup Regulator Unregulated V IN Voltage Pushbutton R1 R2 Note: 1. Required for embedded crystal (MX) package only. M41ST85W SCL SDA WDI RSTIN1 RSTIN2 Reset PFI (1) IRQ/FT/OUT V BAT V SS ...
Page 8
M41ST85W OPERATING MODES The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by imple- menting a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then ...
Page 9
Figure 8. Serial Bus Data Transfer Sequence CLOCK DATA START CONDITION Figure 9. Acknowledgement Sequence START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 10. WRITE Cycle Timing: RTC & External SRAM Control Signals EX E ...
Page 10
M41ST85W READ Mode In this mode the master reads the M41ST85W slave after setting the slave address (see 11.). Following the WRITE Mode Control Bit (R/ W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip ...
Page 11
Figure 12. READ Mode Sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS DATA n+X Figure 13. Alternate READ Mode Sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS WORD S ADDRESS (An) SLAVE ADDRESS P ...
Page 12
M41ST85W WRITE Mode In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol is shown in Figure 14.. Following the START condi- tion and slave address, a logic '0' (R/W=0) is placed on the bus and ...
Page 13
CLOCK OPERATION The eight byte clock register (see 2., page 14) is used to both set the clock and to read the date and time from the clock binary coded decimal format. Tenths/Hundredths of Sec- onds, Seconds, Minutes, ...
Page 14
M41ST85W ® Table 2. TIMEKEEPER Register Map Address D7 D6 00h 0.1 Seconds 01h ST 10 Seconds 02h 0 10 Minutes 03h CEB CB 04h TR 0 05h 0 0 06h 0 0 07h 10 Years 08h OUT FT 09h ...
Page 15
Calibrating the Clock The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error which equates to ...
Page 16
M41ST85W Figure 15. Crystal Accuracy Across Temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Figure 16. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 16/ – ...
Page 17
Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm set- tings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, ...
Page 18
M41ST85W Figure 18. Back-Up Mode Alarm Waveform PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT Watchdog Timer The watchdog timer can be used to detect an out- of-control microprocessor. The ...
Page 19
Square Wave Output The M41ST85W offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 4. Once the ...
Page 20
M41ST85W Power-on Reset The M41ST85W continuously monitors V When V falls to the power fail detect trip point, CC the RST pulls low (open drain) and remains low on power-up for t after V rec CC The RST pin is ...
Page 21
Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an in- ternal reference voltage (1.25V). If PFI is less than the power-fail threshold (V PFI Output (PFO) will go low. This function is intended for use as an undervoltage detector ...
Page 22
M41ST85W t Bit rec Bit D7 of Clock Register 04h contains the t (TR). t refers to the automatic continuation of rec the deselect time after V reaches V CC lows for a voltage settling time before WRITEs may again ...
Page 23
MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those ...
Page 24
M41ST85W DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed ...
Page 25
Table 11. DC Characteristics Sym Parameter Battery Current OSC ON (2) I BAT Battery Current OSC OFF I Supply Current CC1 I Supply Current (Standby) CC2 Input Leakage Current ( Input Leakage Current (PFI) (4) Output Leakage Current ...
Page 26
M41ST85W Figure 21. Bus Timing Requirements Sequence SDA tBUF SCL P S Table 12. AC Characteristics Symbol f SCL Clock Frequency SCL t Time the bus must be free before a new transmission can start BUF ...
Page 27
Figure 22. Power Down/Up Mode AC Waveforms PFD (max) V PFD (min tPD PFO INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) E CON Table 13. Power Down/Up AC Characteristics Symbol (2) V (max) ...
Page 28
M41ST85W PACKAGE MECHANICAL INFORMATION Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline SOH-A Note: Drawing is not to scale. Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical ...
Page 29
Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data Symbol Typ ...
Page 30
M41ST85W Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data Symbol Typ ...
Page 31
Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline SO-E Note: Drawing is not to scale. Table 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data Symbol ...
Page 32
M41ST85W PART NUMBERING Table 18. Ordering Information Scheme Example: Device Type M41ST Supply Voltage and Write Protect Voltage 85W = V = 2.7 to 3.6V; 2.55V CC Package ( SOH28 ( SOX28 Temperature Range 6 = ...
Page 33
REVISION HISTORY Table 20. Document Revision History Date Version August 2000 1.0 First issue 24-Aug-00 1.1 Block Diagram added (Figure 3) t Table removed, cross references corrected 12-Oct-00 1.2 rec 18-Dec-00 2.0 Reformatted, TOC added, and PFI Input Leakage Current ...
Page 34
M41ST85W Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...