M41T11_08 STMICROELECTRONICS [STMicroelectronics], M41T11_08 Datasheet - Page 8

• Manufacturer Part Number: M41T11_08
• Description: Serial real-time clock with 56 bytes of NVRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

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2.1
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2.1.2
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Operation
The M41T11 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
●
●
●
●
●
●
●
●
●
The M41T11 clock continually monitors V
fall below V
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When V
the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. Upon power-up, the device switches from
battery to V
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
1
2
3
4
5
6
7
8
9
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
st
nd
rd
th
th
th
th
th
th
byte: seconds register
byte: day register
byte: date register
byte: month register
byte: years register
byte: control register
- 64
byte: century/hours register
byte: minutes register
SO
CC
th
, the device terminates an access in progress and resets the device address
bytes: RAM
at V
SO
and recognizes inputs.
CC
for an out of tolerance condition. Should V
CC
falls below V
CC
SO
,