M41ST87WMX6F STMICROELECTRONICS [STMicroelectronics], M41ST87WMX6F Datasheet - Page 31
![no-image](/images/no-image-200.jpg)
M41ST87WMX6F
Manufacturer Part Number
M41ST87WMX6F
Description
5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M41ST87WMX6F.pdf
(52 pages)
M41ST87Y, M41ST87W
Keys:
0 = Must be set to zero
32kE = 32 kHz output enable bit
ABE = Alarm in battery backup mode enable bit RS0-RS3 = SQW frequency
AF = Alarm flag (read only)
AFE = Alarm flag enable bit
BL = Battery low flag (read only)
BMB0-BMB4 = Watchdog multiplier bits
CB0-CB1 = Century bits
CLR (1 and 2) = RAM clear bits
CLR (1 and 2)
CLRPW0 = RAM clear pulse width 0 bit
CLRPW1 = RAM clear pulse width 1 bit
FT = Frequency test bit
HT = Halt update bit
OF = Oscillator fail bit
OFIE = Oscillator fail interrupt enable bit
OUT = Output level
PFOD = Power-fail output open drain bit
3.2
EXT
Calibrating the clock
The M41ST87Y/W is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested to not exceed ±35 ppm (parts per million) oscillator
frequency error at 25
month. Even better accuracy can be achieved with higher accuracy crystals. When the
calibration circuit is properly employed, accuracy can be improved to better than ±2 ppm at
25 °C.
The oscillation rate of crystals changes with temperature (see
Therefore, the M41ST87Y/W design employs periodic counter correction. The calibration
circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,
as shown in
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
= RAM clear external bits
Figure 23: Calibration waveform on page
°
C, with ±20 ppm crystals, which translates to about ±1.53 minutes per
Doc ID 9497 Rev 8
RB0-RB1 = Watchdog resolution bits
RPT1-RPT5 = Alarm repeat mode bits
S = Sign bit
SQWE = Square wave enable
SQWOD = Square wave open drain bit
ST = Stop bit
TB (1 and 2) = Tamper bits (read only)
TCHI/TCLO (1 and 2) = Tamper current hi/tamper current low bits
TCM (1 and 2) = Tamper connect mode bits
TDS (1 and 2) = Tamper detect sampling bits
TEB (1 and 2) = Tamper enable bits
THS = Threshold bit
TIE (1 and 2) = Tamper interrupt enable bits
TPM (1 and 2) = Tamper polarity mode bits
TR = t
WDS = Watchdog steering bit
WDF = Watchdog flag (read only)
rec
bit
33. The number of times pulses which
Figure 22 on page
Clock operation
33).
31/52