M48T02_10 STMICROELECTRONICS [STMicroelectronics], M48T02_10 Datasheet - Page 9

• Manufacturer Part Number: M48T02_10
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T02, M48T12
2.2
Figure 5.
Figure 6.
A0-A10
E
W
DQ0-DQ7
A0-A10
E
W
DQ0-DQ7
WRITE mode
The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
WRITE enable controlled, WRITE AC waveform
Chip enable controlled, WRITE AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
Doc ID 2410 Rev 8
tAVWH
tAVEH
EHAX
tWLWH
VALID
tAVAV
VALID
WHDX
tAVAV
tELEH
from chip enable or t
afterward. G should be kept high during WRITE
WLQZ
tDVEH
tDVWH
DATA INPUT
after W falls.
DATA INPUT
tWHDX
WHAX
tEHDX
tWHQX
from WRITE enable prior
tEHAX
tWHAX
DVWH
Operation modes
prior to the
AI01332B
AI01331
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