M48T86PC1E STMICROELECTRONICS [STMicroelectronics], M48T86PC1E Datasheet - Page 20

• Manufacturer Part Number: M48T86PC1E
• Description: 5.0 V PC real-time clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Register B
SET
PIE: periodic interrupt enable
AIE: alarm interrupt enable
UIE: update ended interrupt enable
SQWE: square wave enable
DM: data mode
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When the SET Bit is a '0,' the update transfer functions normally by advancing the counts
once per second. When the SET Bit is written to a '1,' any update transfer is inhibited and
the program may initialize the time and calendar bytes without an update occurring. READ
cycles can be executed in a similar manner. SET is a READ/WRITE bit which is not
modified by RST or internal functions of the M48T86.
The Periodic Interrupt Enable Bit (PIE) is a READ/WRITE bit which allows the Periodic
Interrupt Flag (PF) Bit in Register C to cause the IRQ pin to be driven low (see
page 21
interrupts are generated by driving the IRQ pin low at a rate specified by the RS3-RS0 bits
of Register A. A '0' in the PIE Bit blocks the IRQ output from being driven by a periodic
interrupt, but the Periodic Flag (PF) Bit is still set at the periodic rate. PIE is not modified by
any internal M48T86 functions, but is cleared to '0' on RST.
The Alarm Interrupt Enable (AIE) Bit is a READ/WRITE bit which, when set to a '1,' permits
the Alarm Flag (AF) Bit in Register C to assert IRQ. An alarm interrupt occurs for each
second that the three time bytes equal the three alarm bytes including a “Don't care” alarm
code of binary 1XXXXXXX. When the AIE Bit is set to '0,' the AF Bit does not initiate the IRQ
signal. The RST pin clears AIE to '0.' The internal functions of the M48T86 do not affect the
AIE Bit.
The Update Ended Interrupt Enable (UIE) Bit is a READ/WRITE bit which enables the
Update End Flag (UF) Bit in Register C to assert IRQ. A transition low on the RST pin or the
SET Bit going high clears the UIE Bit.
When the Square Wave Enable (SQWE) Bit is set to a '1,' a square wave signal is driven out
on the SQW pin. The frequency is determined by the rate-selection bits RS3-RS0. When the
SQWE Bit is set to '0,' the SQW pin is held low. The SQWE Bit is cleared by the RST pin.
SQWE is a READ/WRITE bit.
The Data Mode (DM) Bit indicates whether time and calendar information are in binary or
BCD format. The DM Bit is set by the program to the appropriate format and can be read as
required. This bit is not modified by internal function or RST. A '1' in DM signifies binary data
and a '0' specifies Binary Coded Decimal (BCD) data.
for the relationship between PIE and UIE). When the PIE Bit is set to '1,' periodic
Figure 10 on