AD7346B AD [Analog Devices], AD7346B Datasheet - Page 7

• Manufacturer Part Number: AD7346B
• Description: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
• Manufacturer: AD [Analog Devices]

Mnemonic
R /
LOOPBACK
AA-BUF-BP
AA-FLTR-BP
Tx-GAIN-SEL
W R B O T H
Tx-DACOUT Tx-FILT-BP
0
1
0
0
Serial Register SEL[2:0]=000
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
REV PrA
R/
SEL[2] = 0
SEL[1] = 0
SEL[0] = 0
LOOPBACK
AA-BUF-BP
AA-FLTR-BP
Tx-GAIN-SEL
Tx-DACOUT
Tx-LPF-BP
Tx-DRVR-BP
PGA-GC2
PGA-GC1
PGA-GC0
0
0
1
0
Control Reg
When R/
Serial data will subsequently be output onto the DR pin. If R/
at D[11:0] will be written into the register bank addressed by SEL[2:0].
When
high impedance when the transmit channel is powered down.
When this bit is low, the entire receive channel is powered down.
When this bit is high, analog loopback is selected.
When this bit equals 1, the ADC buffer is bypassed.
When this bit equals 1, the receive filter is bypassed.
When Tx-GAIN-SEL equals 1, the output of the transmit filter is attenuated by 6 dB.
The transmit and receive programmable filter corner frequencies are addressed by the 11-bits words
TPFD and RPFD respectively.
filter register if SEL[2:0] = 010.
010. If WRBOTH equals 1 during either of the above conditions, the word in the serial input
register is loaded into both the TFPD and RFPD registers.
= 0
Function
PRELIMINARY TECHNICAL DATA
is high, the register bank addressed by SEL[2:0] is loaded into the output shift register.
Tx-DRVR-BP
0
0
0
1
SEL[2:0]=001
Tx Prog Filt Reg
R/
SEL[2] = 0
SEL[1] = 0
SEL[0] = 1
W R B O T H
TPFD[10]
TPFD[9]
TFPD[8]
TFPD[7]
TFPD[6]
TFPD[5]
TFPD[4]
TFPD[3]
TFPD[2]
TFPD[1]
TFPD[0]
is low, the entire transmit channel is powered down.
= 0
Configuring the Transmit Channel
Control Register Functions
Table 1. Control Register
Configuration
Default. All Components in the Tx channel are used.
The DAC output is seen at the line driver output pins. The line driver
amplifier output is in a high impedance state.
The Tx filter is bypassed. The DACOUT is fed to the PGA. The
filter amplifier output is in a high impedance state.
The filter output is seen at the line driver output pins. The line driver
amplifier output is in a high impedance state.
TPFD data is loaded from the serial input register to the transmit
RPFD data is written to the receive filter register if SEL[2:0] =
RFPD[6]
SEL[2:0]=010
Rx Prog Filt Reg
R/
SEL[2] = 0
SEL[1] = 1
SEL[0] = 0
W R B O T H
RPFD[10]
RPFD[9]
RPFD[8]
RFPD[7]
RFPD[5]
RFPD[4]
RFPD[3]
RFPD[2]
RFPD[1]
RFPD[0]
– 7 –
= 0
SEL[2:0]=011
R/
SEL[2] = 0
SEL[1] = 1
SEL[0] = 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Test Purposes Only
is low, the serial input data located
= 0
The line driver output is
AD5011