ISL5216_05 INTERSIL [Intersil Corporation], ISL5216_05 Datasheet - Page 51
ISL5216_05
Manufacturer Part Number
ISL5216_05
Description
Four-Channel Programmable Digital DownConverter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.ISL5216_05.pdf
(65 pages)
- Current page: 51 of 65
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Electrical Specifications
NOTES:
AC Test Load Circuit
Waveforms
24. The ISL5216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
25. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
R/W Hold Time from Rising Edge of DSTRB
SERIAL CLOCK OUTPUT TIMING (FIGURE 11)
CLK to Serial Data, Sync and SCLK (Divide-by 2 thru 16 Modes)
CLK to SCLK (Divide-by 1 Mode, Note 25)
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 thru 16 Modes, Note 25)
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 25)
ENIB, ENIC, ENID, SYNCI,
AIN, BIN, CIN, DIN, ENIA,
NOTE - TEST HEAD CAPACITANCE, 40pF (TYP)
SWITCH S1 OPEN FOR I
SYNCI(0-3)
SYNCO, INTRPT
51
V
T
A
CC1
= -40
PARAMETER
RESET
= Core Supply: 2.5V ± 0.125V, V
CLK
o
C to 85
CCSB
FIGURE 6. INPUT AND CONTROL TIMING
o
C Industrial (Continued)
AND I
DUT
CCOP
t
CH
ISL5216
C
L
1/f
t
(NOTE)
RW
S
CLK
1
CC2
= I/O Supply: 3.3 ± 0.165V ,
t
DS
t
CL
t
RS
EQUIVALENT CIRCUIT
I
OH
SYMBOL
t
t
t
SKEW1
SKEW2
R/WHR
t
t
PDL
t
PD
PDC
t
DH
±
1.5V
MIN
-2
0
1
-
-
I
OL
MAX
6.5
8
2
3
-
UNITS
July 8, 2005
ns
ns
ns
ns
ns
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