AD9863-50EB AD [Analog Devices], AD9863-50EB Datasheet - Page 39

• Manufacturer Part Number: AD9863-50EB
• Manufacturer: AD [Analog Devices]

Table 24 shows typical output delay times for the AD9863 in the various mode configurations.
Table 24. AD9863 Rx Data Latch Timing
Mode No.
1
2
4
5
7
8
10
Configuration Without Serial Port Interface (Using Mode Pins)
The AD9863 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the
AD9863 without an SPI. Refer to the Configuring with Mode Pins section of the data sheet for more information.
When using the mode pin option, the pins shown in Table 25 are used to configure the AD9863.
Table 25. Using Mode Pin (SPI Disabled) to Configure Timing (SPI_CS, Pin 64, Must be Tied Low)
Clock Mode
Mode 1 (FD)
Mode 4 (HD24)
Mode 7 (HD12)
1
Pin 17 (IFACE2) is an output clock in FD mode.
Mode Name
FD
Optional FD
HD24
Optional HD24
HD12
Optional HD12
Clone
Interpolation
Setting
2×
4×
1×
2×
4×
2×
4×
t
+2.5 ns
+1 ns
+1 ns
+2 ns
−1.5 ns
−0.5 ns
−1.5 ns
+0.5 ns
+0 ns
+1.5 ns
OD
Data Delay [ns]
PLL Setting
2×
4×
Bypassed
2×
4×
2×
4×
Rev. A | Page 39 of 40
FD/HD
Pin 3
1
0
0
Relative to:
Relative to IFACE2 rising edge
Relative to IFACE3 rising edge
Relative To IFACE3 rising edge
IFACE2 (RxSYNC) relative to LSB
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
U12 (RxSYNC) relative to LSB
Relative to IFACE3 rising edge
12/20
Pin 17
N/A
0
1
1
Interp1, Interp0
Pin 1, Pin 2
0, 1
1, 0
0, 0
0, 1
1, 0
0, 1
1, 0
AD9863