AD9863-50EB AD [Analog Devices], AD9863-50EB Datasheet - Page 6

• Manufacturer Part Number: AD9863-50EB
• Manufacturer: AD [Analog Devices]

AD9863
TIMING SPECIFICATIONS
Table 5.
Parameter
INPUT CLOCK
TxPATH DATA
RxPATH DATA
Table 6. Explanation of Test Levels
Level
I
II
III
IV
V
VI
CLKIN2 Clock Rate (PLL Bypassed)
PLL Input Frequency
PLL Ouput Frequency
Setup Time
(HD24 Mode, Time Required Before Data Latching Edge)
Hold Time
(HD24 Mode, Time Required After Data Latching Edge)
Latency 1× Interpolation (Data In Until Peak Output Response)
Latency 2× Interpolation (Data In Until Peak Output Response)
Latency 4× Interpolation (Data In Until Peak Output Response)
Output Delay (HD24 Mode, t
Latency
100% production tested.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
Description
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
OD
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Rev. A| Page 6 of 40
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
Min
1
16
32
Typ
5
−1.5
7
35
83
−1.5
5
Max
200
200
350
Unit
MHz
MHz
MHz
ns (see Clock
Distribution Block
section)
ns (see Clock
Distribution Block
section)
DAC clock cycles
DAC clock cycles
DAC clock cycles
ns ( see Clock
Distribution Block
section)
ADC clock cycles