AD15252/PCB AD [Analog Devices], AD15252/PCB Datasheet

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AD15252/PCB

Manufacturer Part Number
AD15252/PCB
Description
12-Bit, 65 MSPS, Dual ADC
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
12-bit, 65 MSPS dual ADC
Differential input with 100 Ω input impedance
Full-scale analog input: 296 mV p-p
170 MHz, 3 dB bandwidth
SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN)
SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN)
435 mW per channel
Dual parallel output buses
Out-of-range indicators
Independent clocks
Duty cycle stabilizer
Twos complement or offset binary data format
APPLICATIONS
Antijam GPS receivers
Wireless and wired broadband communications
Communications test equipment
GENERAL DESCRIPTION
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital
converter (ADC). It features a differential front-end
amplification circuit followed by a sample-and-hold amplifier
and multistage pipeline ADC. It is designed to operate with a
3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input
is fully differential, ac-coupled, and terminated in 100 Ω input
impedances. The full-scale differential signal input range is
296 mV p-p.
Two parallel, 12-bit digital output buses provide data flow from
the ADCs. The digital output data is presented in either straight
binary or twos complement format. Out-of-range (OTR) signals
indicate an overflow condition, which can be used with the
most significant bit to determine low or high overflow. Dual
single-ended clock inputs control all internal conversion cycles.
A duty cycle stabilizer allows wide variations in the clock duty
cycle while maintaining excellent performance. The AD15252 is
optimized for applications in antijam global positioning
receivers and is well suited for communications applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1.
2.
3.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
PDWNA
PDWNB
OTR_A
OEB_A
OEB_B
OTR_B
Dual 12-bit, 65 MSPS ADC with integrated analog signal
conditioning optimized for antijam global positioning
system receiver (AJ-GPS) applications.
Operates from a single 3.3 V power supply and features a
separate digital output driver supply to accommodate 2.5 V
and 3.3 V logic families.
Packaged in a space-saving 8 mm × 8 mm chip scale
package ball grid array (CSP_BGA) and is specified over
the industrial temperature range (–40°C to +85°C).
CLKA
CLKB
DFS
INA
INB
12-Bit, 65 MSPS, Dual ADC
FUNCTIONAL BLOCK DIAGRAM
© 2005 Analog Devices, Inc. All rights reserved.
Figure 1.
LPF
LPF
AD15252
AD15252
www.analog.com
DATA
BUS A
DATA
BUS B

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AD15252/PCB Summary of contents

Page 1

FEATURES 12-bit, 65 MSPS dual ADC Differential input with 100 Ω input impedance Full-scale analog input: 296 mV p-p 170 MHz bandwidth SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN) SFDR (−9 dBFS): ...

Page 2

AD15252 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 11 Analog Input ............................................................................... 11 Voltage Reference ....................................................................... 11 REVISION ...

Page 3

ELECTRICAL CHARACTERISTICS AVDD = 3.3 V, DRVDD = 2.5 V, encode = 65 MSPS, CLK_A = CLK_B, AIN = −9 dBFS differential input, T noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) ...

Page 4

AD15252 Parameter SIGNAL-TO-NOISE RATIO (SNR MHz INPUT f = 110 MHz INPUT f = 140 MHz INPUT SINAD MHz INPUT f = 110 MHz INPUT f = 140 MHz INPUT THD ...

Page 5

ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AGND DRVDD to DRGND DRGND to AGND DRVDD to AVDD Analog Inputs Digital Outputs CLK Operational Case Temperature Storage Temperature Range Lead Temperature: Infrared, 15 sec ESD CAUTION ESD (electrostatic discharge) sensitive ...

Page 6

AD15252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic A1 VINA A2 VINA H1 VINB H2 VINB B4 CLK_A G4 CLK_B C4 PDWN_A F4 PDWN_B A4 OTR_A E8 OTR_B A3 VCM_A H3 VCM_B D4 OEB_A ...

Page 7

Pin No. Mnemonic F6 D07_B H8 D06_B G7 D05_B H7 D04_B G6 D03_B H6 D02_B G5 D01_B H5 D00_B AVDD B1 to B3, D3 AGND D6, E6 DRVDD D5, E5 DRGND ...

Page 8

AD15252 TYPICAL PERFORMANCE CHARACTERISTICS 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 10 100 FREQUENCY (MHz) Figure 3. Gain Flatness 0 –0.25 –0.50 –0.75 –1.00 –1.25 –1.50 –1.75 –2.00 –2.25 –2.50 –2.75 120 125 130 ...

Page 9

FREQUENCY (MHz) Figure 9. Single-Tone SNR/SFDR vs. f 64.6 64.4 64.2 64.0 63.8 63.6 63.4 63.2 63.0 70 110 FREQUENCY (MHz) Figure 10. Single-Tone SINAD vs –68 –70 –72 –74 ...

Page 10

AD15252 0 1 –10 –20 –30 –40 –50 –60 –70 – –90 –100 –110 –120 –130 0 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 FREQUENCY (MHz) Figure 15. Single-Tone FFT of Channel B Digitizing f While ...

Page 11

THEORY OF OPERATION The AD15252 consists of two high performance ADC channels. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each path consists of a differential front end amplification circuit followed by ...

Page 12

AD15252 A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered. Because the buffer and voltage reference remain powered, the wake-up time ...

Page 13

PCB AND EVALUATION BOARD Figure 21. AD15252 Evaluation Board Top Silk Figure 22. AD15252 Evaluation Board Top Paste Figure 23. AD15252 Evaluation Board Top Mask Figure 24. AD15252 Evaluation Board Top Signal Rev Page AD15252 ...

Page 14

AD15252 Figure 25. AD15252 Evaluation Board Power Plane Figure 26. AD15252 Evaluation Board Ground Plane Figure 27. AD15252 Evaluation Board Bottom Signal Figure 28. AD15252 Evaluation Board Bottom Mask Rev Page ...

Page 15

Figure 29. AD15252 Evaluation Board Bottom Paste Rev Page AD15252 ...

Page 16

AD15252 Figure 30. AD15252 Evaluation Board Schematic: Analog Front End ADC DRVDD D6 DRVDD E6 AVDD F3 AVDD F2 AVDD F1 AVDD C3 AVDD C2 AVDD PRI SEC 4 3 TC1-1-13M Rev Page 16 ...

Page 17

R13 150Ω DATACLK_A R14 150Ω OTR_A R20 150Ω D06_A R19 150Ω D07_A R18 150Ω D08_A R17 150Ω 10 D09_A R16 150Ω D10_A R15 150Ω D11_A LSB0_AX R28 DNI LSB0_A 1 R27 DNI LSB1_A 19 LSB1_AX R26 150Ω D00_A ...

Page 18

AD15252 C5 J3 0.1μF R83 R83 49.9Ω 49.9Ω ANALOG +3.3V AGND Y1 C14 JP8 0.1μ AGND VF140SHHL-65MHz XTAL A = ENABLE B = DISABLE C6 J4 0.1μF R84 49.9Ω AGND U6 ...

Page 19

... OUTLINE DIMENSIONS 1.70 1.55 1.35 ORDERING GUIDE Model Temperature Range AD15252BBC −40°C to +85°C AD15252/PCB 8.10 8. BALL A1 CORNER 5.60 BSC SQ TOP VIEW 0.80 BSC BOTTOM VIEW DETAIL A DETAIL A 0.34 NOM 0.25 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-BA Figure 33. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA] ...

Page 20

AD15252 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05154–0–8/05(0) Rev Page ...

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