AD15252/PCB AD [Analog Devices], AD15252/PCB Datasheet - Page 11

• Manufacturer Part Number: AD15252/PCB
• Description: 12-Bit, 65 MSPS, Dual ADC
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The AD15252 consists of two high performance ADC channels.
The dual ADC paths are independent, except for a shared
internal band gap reference source, VREF. Each path consists of
a differential front end amplification circuit followed by a
sample-and-hold amplifier and multistage pipeline ADC.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment
of the output voltage swing.
ANALOG INPUT
Each analog input is fully differential, allowing sampling of
differential input signals. The differential input signals are ac-
coupled and terminated in 100 Ω input impedances. The full-
scale differential signal input range is 296 mV p-p.
VOLTAGE REFERENCE
The internal voltage reference of the ADC is pin strapped to a
fixed value of 0.5 V. A 10 μF capacitor should be used between
REFT and REFB.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, can be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD15252 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels
asynchronously can significantly degrade performance. In some
applications, it is desirable to skew the clock timing of adjacent
channels. The AD15252’s separate clock inputs allow clock
timing skew (typically ±1 ns) between the channels without
significant performance degradation.
The AD15252 contains two internal clock duty cycle stabilizers
(DCS), one for each converter, which retime the nonsampling
edge, providing an internal clock with a nominal 50% duty
cycle. Input clock rates of over 40 MHz can use the DCS so that
a wide range of input clock duty cycles can be accommodated.
Maintaining a 50% duty cycle clock is particularly important in
high speed applications, when proper track-and-hold times for
the converter are required to maintain high performance.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any change to the sampling
frequency requires approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
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High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated by
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter can affect the dynamic range of the AD15252, it is
important to minimize input clock jitter. The clock input
circuitry should use stable references, for example, using analog
power and ground planes to generate the valid high and low
digital levels for the AD15252 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD15252 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
where:
N is the number of bits changing.
C
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increase with clock frequency.
Either channel of the AD15252 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The minimum standby power is achieved when both channels
are placed into full power-down mode using PDWN_A =
PDWN_B = high. Under this condition, the internal references
are powered down. When either or both of the channel paths
are enabled after a power-down, the wake-up time is directly
related to the recharging of the REFT and REFB decoupling
capacitors and to the duration of the power-down. Typically, it
takes approximately 5 ms to restore full operation with fully
discharged 10 μF decoupling capacitors on REFT and REFB.
LOAD
SNR Degradation = 20 × log 10 (1/2 × p × f
I
DRVDD
is the average load on the digital pins that changed.
= V
DRVDD
INPUT
× C
) due only to aperture jitter (t
LOAD
× f
CLOCK
× N
J
, represents the root-
INPUT
AD15252
J
) can be
× t
J
)