AD15452/PCB AD [Analog Devices], AD15452/PCB Datasheet - Page 13

• Manufacturer Part Number: AD15452/PCB
• Description: 12-Bit 65 MSPS Quad A/D Converter with Integrated Signal Conditioning
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The AD15452 consists of four high performance ADC
channels. Each channel is independent of each other with the
exception of a shared internal reference source, VREF, and
sample clock. The channels consist of a differential front-end
amplification circuit followed by a low-pass filter and a multi-
stage pipeline ADC. The quantized outputs from each stage are
combined into a 12-bit result. The output staging block aligns
the data, carries out the error correction, and passes the data to
the output buffers; the data is then serialized and aligned to the
frame and output clock.
ANALOG INPUTS
Each analog input is fully differential, allowing sampling of
differential input signals. The differential input signals are ac-
coupled and terminated in 100 Ω input impedances. The full-
scale differential signal input range is 296 mV p-p.
VOLTAGE REFERENCE
The AD15452 reference voltage is set internally to 0.5 V. The
VREF pin and SENSE pin are used to decouple the 0.5 V
reference. The VREF pin and SENSE pin must be shorted
together and then decoupled with a 10 μF capacitor to AGND.
Ideally, this capacitor should be placed as close to the pins as
possible. The REFT pin and the REFB pin must have a 10 μF
capacitor placed between the two pins.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Typically, a 5% tolerance is
required on the clock duty cycle to maintain dynamic perform-
ance characteristics. The AD15452 has a self-contained clock
duty cycle stabilizer that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD15452.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for shifting the serial data out. Consequently, any
change to the sampling frequency requires a minimum of 100
clock periods to allow the PLL to reacquire and lock to the
new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated with the following equation:
SNR degradation = 20 × log10 [1/2 × π × f
A
) due only to aperture jitter (t
A
× t
A
) can be
A
]
Rev. 0 | Page 13 of 16
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Applications that require undersampling are particularly
sensitive to jitter.
The clock input is treated as an analog signal in cases where
aperture jitter can affect the dynamic range of the AD15452.
Power supplies for clock drivers are separated from the ADC
output driver supplies to avoid modulating the clock signal with
digital noise. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or other methods) then the original
clock at the last step should retime it.
DIGITAL OUTPUTS
The AD15452 differential outputs conform to the ANSI-644
LVDS standard. To set the LVDS bias current, place a resistor
(RSET is nominally equal to 4.0 kΩ) to ground at the
LVDSBIAS pin. The RSET resistor current is derived on-chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver. To adjust the differential signal swing, simply change
the resistor to a different value, as shown in Table 5.
Table 5. LVDSBIAS Differential Output Swing
RSET
3.6
3.9
4.3
The AD15452 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capabil-
ity for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. It is recommended to keep the trace length no longer
than 12 inches and to keep differential output traces close
together and at equal lengths.
The format of the output data can be selected as offset binary. A
quick example of the output coding format can be found in
Table 6.
Table 6. Digital Output Coding
Code
4095
2048
2047
0
kΩ
kΩ
kΩ
(Default)
(VIN+) − (VIN−) Input
Span = 296 V p-p (V)
0.147
0
−0.000072
−0.148
Differential Output Swing
375 mV p-p
350 mV p-p
325 mV p-p
Digital Output Offset
Binary (D11...D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
A
, represents the root
AD15452