AD9883/PCB AD [Analog Devices], AD9883/PCB Datasheet - Page 11

• Manufacturer Part Number: AD9883/PCB
• Description: 110 MSPS Analog Interface for Flat Panel Displays
• Manufacturer: AD [Analog Devices]

Standard
VGA
SVGA
XGA
SXGA
Timing
The following timing diagrams show the operation of the AD9883.
The Output Data Clock signal is created so that its rising edge
always occurs between data transitions, and can be used to latch
the output data externally.
There is a pipeline in the AD9883, which must be flushed before
valid data becomes available. This means four data sets are
presented before valid data is available.
DATACK
HSOUT
DATA
Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
DATACK
ADCCK
HSYNC
HSOUT
RGB
D
PxCK
Resolution
640 × 480
800 × 600
1024 × 768
1280 × 1024
OUTA
t
HS
IN
CYCLE
t
SKEW
P0
t
PER
P1
5-PIPE DELAY
P2
Refresh
Rate
60 Hz
72 Hz
75 Hz
85 Hz
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
60 Hz
P3
P4
P5
Horizontal
Frequency
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
64.0 kHz
D0
P6
D1
P7
Hsync Timing
Horizontal Sync (Hsync) is processed in the AD9883 to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9883. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
D2
VARIABLE DURATION
D3
Pixel Rate
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
108.000 MHz
D4
D5
D6
VCORNGE
00
00
00
00
00
01
01
01
01
01
10
10
10
10
10
D7
AD9883
CURRENT
101
110
110
110
110
100
100
100
101
110
100
100
100
100
110