AD9883/PCB AD [Analog Devices], AD9883/PCB Datasheet - Page 18

• Manufacturer Part Number: AD9883/PCB
• Description: 110 MSPS Analog Interface for Flat Panel Displays
• Manufacturer: AD [Analog Devices]

AD9883
0F
0F
10
10
10
2 Seek Mode Override
This bit is used to either allow or disallow the low-power
mode. The low-power mode (seek mode) occurs when
there are no signals on any of the Sync inputs.
Select
1
0
The default for this register is 1.
1 PWRDN
This bit is used to put the chip in full power down. See
the section on power management for details of which
blocks are actually powered down.
Select
0
1
The default for this register is 1.
7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10 mV
and the maximum setting equaling 330 mV.
The default setting is 23 and corresponds to a threshold
value of 0.15 V.
2 Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 37.
Clamp
0
1
The default setting for this register is 0.
1 Green Clamp Select
A bit that determines whether the green channel is
clamped to ground or to midscale.
Clamp
0
1
The default setting for this register is 0.
Table XXIV. Green Clamp Select Settings
Table XXI. Seek Mode Override Settings
Table XXIII. Red Clamp Select Settings
Table XXII. Power-Down Settings
Result
Power-Down
Normal operation
Function
Clamp to Ground
Clamp to Midscale, (Pin 37)
Function
Clamp to Ground
Clamp to Midscale, (Pin 37)
Result
Allow Seek Mode
Disallow Seek Mode
10
11
12
13
14
14
0 Blue Clamp Select
A bit that determines whether the blue channel is clamped
to ground or to midscale.
Clamp
0
1
The default setting for this register is 0.
7:0 Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulse width. Note: the sync separator threshold uses an
internal dedicated clock with a frequency of approxi-
mately 5 MHz.
The default for this register is 32.
7-0 Pre-Coast
This register allows the coast signal to be applied prior to
the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7-0 Post-Coast
This register allows the coast signal to be applied follow-
ing to the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7 Hsync Detect
This bit is used to indicate when activity is detected on
the Hsync input pin, (Pin 30). If Hsync is held high or
low, activity will not be detected.
Detect
0
1
The sync processing block diagram shows where this
function is implemented.
6 AHS – Active Hsync
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or sync-on-green). Bits 7 and 1
in this register are what determine which source is used. If
both Hsync and SOG are detected, the user can determine
which has priority via Bit 3 in register 0EH. The user can
override this function via Bit 4 in register 0EH. If the
override bit is set to Logic 1, then this bit will be forced to
whatever the state of Bit 3 in register 0EH is set to.
Table XXV. Blue Clamp Select Settings
Table XXVI. Hsync Detection Results
Function
Clamp to Ground
Clamp to Midscale, (Pin 37)
Function
No Activity Detected
Activity Detected