AD7766-1 AD [Analog Devices], AD7766-1 Datasheet - Page 18

• Manufacturer Part Number: AD7766-1
• Description: 24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs
• Manufacturer: AD [Analog Devices]

AD7767
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple ADCs
on a single data line. This feature is especially useful for reduc-
ing component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register where data is clocked on the falling edge of SCLK.
The block diagram in Figure 36 shows the way in which devices
must be connected in order to achieve daisy chain functionality.
This scheme operates by passing the output data of the SDO pin
of an AD7767 device to the SDI input of the next AD7767 device
in the chain. The data then continues through the chain until it
is clocked onto the SDO pin of the first device on the chain.
READING DATA IN DAISY CHAIN MODE
An example of a daisy chain of four AD7767 devices is shown in
Figure 36 and Figure 37. In the case illustrated in Figure 36, the
output of AD7767 (A) is the output of the full daisy chain. The
last device in the chain (AD7767 (D)) has its serial data in (SDI)
pin connected to ground. All the devices in the chain must use
common MCLK, SCLK, CS , and SYNC / PD signals.
To enable the daisy chain conversion process, apply a common
SYNC / PD pulse to all devices, synchronizing all the devices in
the chain (see the Power-Down, Reset, and Synchronization
section).
After applying a SYNC / PD pulse to all the devices, there is a
delay (as listed in Table 7) before valid conversion data appears
at the output of the chain of devices. As shown in Figure 37,
the first conversion result is output from the device labeled
AD7767 (A). This 24-bit conversion result is followed by the
conversion results from the devices B, C, and D, respectively,
with all conversion results output in an MSB first sequence. The
stream of conversion results is clocked through each device in
the chain and is eventually clocked onto the SDO pin of the
AD7767 (A) device. The conversion results of the all the devices
in the chain must be clocked onto the SDO pin of the final
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device in the chain while its DRDY signal is active low. This is
illustrated in the example shown where the conversion results
from devices A, B, C, and D are clocked onto SDO (A) in the
time between the falling edge of DRDY (A) and the rising edge
of DRDY (A).
CHOOSING THE SCLK FREQUENCY
As shown in Figure 36, the number of SCLK falling edges that
occur during the period when DRDY (A) is active low must
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).
The period of SCLK (t
length using a known common MCLK frequency must
therefore be established in advance. Note that the maximum
SCLK frequency is governed by t
Specifications table for different V
In the case where CS is tied logic low,
where:
K is the number of AD7767 devices in the chain.
t
t
In the case where CS is used in the daisy chain interface,
where:
K is the number of AD7767 devices in the chain.
Note that the maximum value of SCLK is governed by t
specified in the Timing Specifications table for different V
voltages.
SCLK
READ
is the period of the SCLK.
equals
t
t
SCLK
SCLK
≤
≤
t
⎡
⎢
⎣
⎡
⎢
⎣
DRDY
(
24
t
t
READ
READ
×
− t
K
) (
−
⎤
⎥
⎦
5
24
.
SCLK
t
6
×
) required for a known daisy chain
+
K
t
7
+
t
8
13
and is specified in the Timing
DRIVE
)
⎤
⎥
⎦
voltages.
8
and is
DRIVE
(1)
(2)